[ANN] XMODZ-Fast modulo reduction VHDL IPs

Thank you, Mr. Nikolaos Kavvadias, for the SPAM!

I'll remember that next time my company evaluates IP vendors.

JJS

Hi John,

I think that such kind of announcements (straight, informative and to the point) are far from spam.

Personally, I find myself reading such "ANN"s, most of the time.

I didn't intend to make you feel offended, just to let people know what kind of IP is available as a standalone offering.

If you have any technical questions, observations or suggestions I will be glad to answer them.

Kind regards, Nikolaos Kavvadias

Nowadays, I think we should be happy for every bit of traffic we get here a t comp.arch.fpga ;-)

On-topic: I am not sure if your IP allows for arbitrary Zs (e.g. x MOD 253) or just s pecial ones.

About a year ago I had to do mod 3 and mod 7 operations on about 12b wide o perands. After thinking almost a complete day, I came up with a solution th at was extremely fast and small (I think just about 20 LEs for each case). But my approach would not work for every modulo.

Regards,

Thomas

Hi Thomas,

at comp.arch.fpga ;-)

I feel this way too ^_^

special ones.

The modv IP (x mod by an independent variable, z) allows you to use any z.

The modk IP has to be fixed at compile/elaboration time to a specific constant K. However, you can change the value of K (it is a generic) and therefore modk can be configured to support any positive integer constant.

operands. After thinking almost a complete day, I came up with a solution that was extremely fast and small (I think just about 20 LEs for each case) . But my approach would not work for every modulo.

Yes, you are right. mod 3, 7, 10, 12 are some of the most popular constants. A general circuit description has the benefit of removing all this redesigning burden from you.

Thomas, have you read the product brief and the documentation? Here are corresponding links to both:

I also think that is possible to provide Modelsim (or GHDL on Linux) compiled files (not the HDL itself) for evaluation (for free). And/or to supply a synthesis report for your specific cases, just for reference purposes.

Best regards Nikolaos Kavvadias

Hi Thomas,

this is a summary of synthesis reports for XMODZ on your suggested configurations.

The results have been obtained with Xilinx XST/ISE 12.3 for a small Virtex-6 device (XC6VLX75T).

"REG" designs have pipeline registers at each stage, "COMB" designs only have registers at the output.

(This table is best viewed with a monospace font).

+--------+------+----------+------------+------------+------------ +-------------+ | Design | Mode | Latency | Throughput | Min. clk per| LUTs | Regs | | | | | | | | | +--------+------+----------+------------+------------+------------ +-------------+ | modv | REG | 14 | 1 | 3.5 ns | 174 | 235 | +--------+------+----------+------------+------------+------------ +-------------+ | modv | COMB | 1 | 1 | 32 ns | 154 | 13 | +--------+------+----------+------------+------------+------------ +-------------+ | modk=3 | REG | 12 | 1 | 2.53 ns | 111 | 98 | +--------+------+----------+------------+------------+------------ +-------------+ | modk=3 | COMB | 1 | 1 | 5.76 ns | 36 | 13 | +--------+------+----------+------------+------------+------------ +-------------+ | modk=7 | REG | 11 | 1 | 2.53 ns | 112 | 94 | +--------+------+----------+------------+------------+------------ +-------------+ | modk=7 | COMB | 1 | 1 | 21.86 ns | 88 | 13 | +--------+------+----------+------------+------------+------------ +-------------+

Best regards Nikolaos Kavvadias