Field-Programmable Gate Arrays

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What is 'drive strength' for? (Spartan 3)

Hi everyone, I'm building a circuit that will be driving quite a few (>100) LEDs, multiplexed into 3 or 4 groups, so up...
4 comments posted 20yrs
posted by p.boven
4 comments posted 20yrs posted by p.boven

Xilinx LVDS termination resistor

How do you turn the 100 ohm resistor on for an LVDS input? I am using the HDR2 header on an ML402 dev board. Brad Smallr...
4 comments posted 20yrs
posted by bradsmallridge
4 comments posted 20yrs posted by bradsmallridge

Lattice XP simple simulator

Is it possible to simulate an extremely simple VHDL design generated by ispLEVER Starter? It is composed of an EBR RAM...
1 comments posted 20yrs
posted by wyderski
1 comments posted 20yrs posted by wyderski

CP2101 <-> Printer?

Hallo, I have bought a Virtex-4FX Mini Module + Baseboard from Memec. On the board there is a USB to serial bridge, Sila...
1 comments posted 20yrs
posted by marcotoschi
1 comments posted 20yrs posted by marcotoschi

ISE WebPack Clock Signals

HI i'm working on a project where I get the following warning message: -----------------------------------+------------...
1 comments posted 20yrs
posted by u_stadler
1 comments posted 20yrs posted by u_stadler

Handel-C & DK3

Hi all. I tried to build a project in DK. Compiling is OK but i think i have a problem at the linkage. The output shows...
0 comments posted 20yrs
posted by camillo79
0 comments posted 20yrs posted by camillo79

DigitalRadioMondiale

Hi All, Has anyone made some experiences with fpga and drm. I'm looking for informations and papers to set up my own pro...
1 comments posted 20yrs
posted by reverse_engineer
1 comments posted 20yrs posted by reverse_engineer

disappear silicore

Hi. I have interest with VME bus. Google teach me that silicore made VME core. But I can't connect silicore website. Wha...
0 comments posted 20yrs
posted by false0
0 comments posted 20yrs posted by false0

S3e starter kits available

According to the front page of xilinx's site but not yet in the web shop. http://www.xilinx.com/xlnx/xebiz/designResour...
19 comments posted 20yrs
posted by news
19 comments posted 20yrs posted by news

serial configuration of Spartan 3 FPGA

I am currently developing a system where a user can configure an Spartan 3 FPGA from a Atmega 128(serial configuration)...
0 comments posted 20yrs
posted by yaj_n
0 comments posted 20yrs posted by yaj_n

Using Synplicity to synthesize EDK user IP's

Hey all, I am trying to play around with Synplify and an EDK project I have already implemented solely in the EDK. I ha...
4 comments posted 20yrs
posted by mottoblatto
4 comments posted 20yrs posted by mottoblatto

Virtex-4 CCLK termination

Hello all, I am new to this group, but it has already been a great resource.. thanks to all who post advice and suggest...
5 comments posted 20yrs
posted by shogmic
5 comments posted 20yrs posted by shogmic

ERROR:iMPACT:585

Hello, I seem to have a problem while downloading the design on ML300 trough the JTAG cable. I searched it over the net...
1 comments posted 20yrs
posted by nitesh.guinde
1 comments posted 20yrs posted by nitesh.guinde