Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15253 Threads Posts
to

Verilog! How to work with modules?

Hello! 1.sorry for my poor english 2.i have the following diagram to implement in verilog: http://elf.cs.pub.ro/ac/wiki...
0 comments posted 12yrs
posted by kristo.godari
0 comments posted 12yrs posted by kristo.godari

LCD test on Spartan 3E FPGA

Hi, I got a problem that I cannot understand how to display on the LCD of Sp artan 3E FPGA. Then, how to get the inputs...
4 comments posted 12yrs
posted by ttungl
4 comments posted 12yrs posted by ttungl

microZed adventures

We're into this signal processing project, using a microZed/ZYNQ thing as the compute engine. After a week or so of wor...
24 comments posted 12yrs
posted by jjlarkin
24 comments posted 12yrs posted by jjlarkin

Mill: FPGA version?

I've been wondering if there could be a successful (not too large, reasonable clock frequency) soft-core FPGA version o...
6 comments posted 12yrs
posted by jhallen
6 comments posted 12yrs posted by jhallen

FPGA Cryptosystem

Hello all Proposed idea from my research to date: Two FPGA encryption modules: Both will have an identical encryption a...
9 comments posted 12yrs
posted by cyounge28
9 comments posted 12yrs posted by cyounge28

Cyclone V hard memory controller

Hi, I try to implement a DDR3 hard memory controller in a Cyclone v device a 5CGXFC3B6F23C7. I created an DDR3 hard mem...
5 comments posted 12yrs
posted by rf.baumgartner
5 comments posted 12yrs posted by rf.baumgartner

Qsys and clock crossings

I'd love if someone could tell me if what I've found is as stupid as I think it is, or far cleverer than I am. So I'm p...
4 comments posted 12yrs
posted by rgaddi
4 comments posted 12yrs posted by rgaddi

legacy Xilinx software

I've been using Ise WebPack 10.1 for some time, as it is the last version that supported the Spartan 2E chips. I don't...
13 comments posted 12yrs
posted by jmelson
13 comments posted 12yrs posted by jmelson

generating clocks

Hi I am using actel fpga proasic3E A3PE1500. I need to generate 3 clocks of 15 0MHz, 112.5MHz and 14.063MHz. I can't pr...
6 comments posted 12yrs
posted by eyecatcherdear
6 comments posted 12yrs posted by eyecatcherdear

how does PC communicate with FPGA?

Hi, I am unable to understand that how a PC communicate with FPGA. I have used Xilinx software to implement codes and t...
2 comments posted 12yrs
posted by koyel.aphy
2 comments posted 12yrs posted by koyel.aphy

built in adc in fpga????

hi guys, i was wondering whether can i have built in adc in fpga with good (say 12 or 14 bit) resolution and 0-5v input...
6 comments posted 12yrs
posted by shri.gotur
6 comments posted 12yrs posted by shri.gotur