Field-Programmable Gate Arrays

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Worth reading in Field-Programmable Gate Arrays

Altera Primitives Library

Hello, I like to be able to instantiate FPGA primitives directly in my VHDL in ord er to get fine control of a design a...
1 comments posted 12yrs
posted by padudle
1 comments posted 12yrs posted by padudle

addsubs on FPGA

Hi, I have a query on the RTL designing for addsub based implementations. I heard that addsubs are not preferred on FPG...
10 comments posted 12yrs
posted by sh.vipin
10 comments posted 12yrs posted by sh.vipin

register naming

Hello, is there a special term for a register that is not required to preserve its content longer than the next clock c...
6 comments posted 12yrs
posted by 24789
6 comments posted 12yrs posted by 24789

Optimising pin allocation

New to FPGAs, not much understanding of what goes on inside them, and I may never get very far in that direction. I'm b...
4 comments posted 12yrs
posted by bv
4 comments posted 12yrs posted by bv

Simple Telephone Conversation on Fpga board and SSD

Hello, ? have a code like this and i have to use SSD for outputs. module telephoneConversation(clock, reset, caller, ca...
0 comments posted 12yrs
posted by mertserimer
0 comments posted 12yrs posted by mertserimer

Use of latches in FSMs

Hello, I have read in many places that the outputs of a finite state machine must be set to their default values in ord...
6 comments posted 12yrs
posted by ehsan.hosseini
6 comments posted 12yrs posted by ehsan.hosseini

PPC 405 communication with custom IP ml403

Hi Everyone! I am trying to simulate a chemical reaction in FPGA. My basic FPGA architecure consists of 3 processes: --...
0 comments posted 12yrs
posted by khan990
0 comments posted 12yrs posted by khan990

ppc405 communication with custom ip ml403

Hi Everyone! I am trying to simulate a chemical reaction in FPGA. My basic FPGA architecure consists of 3 processes: --...
2 comments posted 12yrs
posted by khan990
2 comments posted 12yrs posted by khan990

New Cloud Based VHDL Simulator-Tarang

Tarang EDA has launched Cloud based VHDL functional verification tool to quickly with many new features which are not p...
2 comments posted 12yrs
posted by neer4j.iit.delhi
2 comments posted 12yrs posted by neer4j.iit.delhi

XC17V08VQ44I or XC17V16VQ44I

I am actively searching for either XC17V08VQ44I or XC17V16VQ44I 0 Xilinx co nfiguration PROMS. I have an OEM customer t...
1 comments posted 12yrs
posted by tiffaniecrocker
1 comments posted 12yrs posted by tiffaniecrocker

BUFG Issue on Virtex 5 FPGA

Folks, I observe a curious problem on my FPGA Build on Virtex 5 FPGA and would lik e to understand if any of you had se...
0 comments posted 12yrs
posted by venkat.japan
0 comments posted 12yrs posted by venkat.japan

Implementing multiple interrupts

Hi all. Some time ago, I designed a small and simple CPU to go into a project I am sort-of working on (when can I steal...
12 comments posted 12yrs
posted by akuktin
12 comments posted 12yrs posted by akuktin