who know what is the problem

who know what is the problem: those four error

C:\copy_project\exemple6\top_ise>map processor_stub.ngd Release 8.1.03i - Map I.27 Copyright (c) 1995-2005 Xilinx, Inc. All rights reserved. Using target part "4vfx12ff668-10". Mapping design into LUTs... ERROR:LIT:248 - CASCADEINA pin of RAMB16 symbol

"top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/physical_group_BRAM_Di n_A/ramb16_0" can be sourced only from a CASCADEOUTA of a different RAMB16. Also, the CASCADEOUTA pin on a RAMB16 can source only a single CASCADEINA pin of a different RAMB16. ERROR:LIT:249 - CASCADEINB pin of RAMB16 symbol

"top/plb_bram_if_cntlr_1_bram/plb_bram_if_cntlr_1_bram/physical_group_BRAM_Di n_A/ramb16_0" can be sourced only from a CASCADEOUTB of a different RAMB16. Also, the CASCADEOUTB pin on a RAMB16 can source only a single CASCADEINB pin of a different RAMB16. ERROR:LIT:301 - EMACDCRACK pin of PPC405_ADV symbol top/ppc405_0/ppc405_0/PPC405_ADV_i can be driven only by pin EMACDCRACK of an EMAC. ERROR:LIT:304 - EMACDCRDBUS bus of PPC405_ADV symbol top/ppc405_0/ppc405_0/PPC405_ADV_i can be driven only by bus EMACDCRDBUS of an EMAC. Errors found during logical drc.

thanks advance

read the Virtex4 user's guide chapter on using BRAM. The cascade in/out can only be connected directly to one other BRAM. If you are not using them, leave them open.