Field-Programmable Gate Arrays

ANNC: VHDL Coding for FPGA Webcast

Lattice is holding a webcast tomorrow, Wednesday, June 14, "Optimizing VHDL Coding for More Efficient FPGA Synthesis."...

1 comments posted 20yrs

posted by bart.borosky

1 comments posted 20yrs posted by bart.borosky

IDELAY clock spec. in Xilinx V4

Hi, Can anyone point me to the spec. for the maximum clock frequency for the CLKDIV pin of the IDELAY block in Virtex 4...

9 comments posted 20yrs

posted by symon_brewer

9 comments posted 20yrs posted by symon_brewer

Virtex-4 FX12: Mini module board from avnet

Hi, I am using the virtx-4 mini module board from Avnet to implement some designs. Howeever I am not able to compile th...

0 comments posted 20yrs

posted by vivek.menon79

0 comments posted 20yrs posted by vivek.menon79

FSM state minimization with ISE?

Hi everybody, I just tried to minimize a simple statemachine with ISE8.1 and wondered that there is no effect, while th...

15 comments posted 20yrs

posted by nix

15 comments posted 20yrs posted by nix

Can i use "burstcount" in my userlogic while using Altera SOPC builder 5.1?

Hi, All! When adding my userlogic in component editor, i can't find the singal type "burstcount". Does Altera SOPC build...

0 comments posted 20yrs

posted by xuweijun1983

0 comments posted 20yrs posted by xuweijun1983

Looking for patent attorney specialized in programmable logic

Looking for a qualified patent attorney/agent specialized in programmable logic technology to file FPGA architecture an...

4 comments posted 20yrs

posted by htchang

4 comments posted 20yrs posted by htchang

Virtex4 DCM in DRP mode

Hi all! I made a clocking module for Virtex4FX12 that accepts 66MHz from DCM0 (FX output at 6/9 ratio from 100MHz). Out...

3 comments posted 20yrs

posted by ales.gorkic

3 comments posted 20yrs posted by ales.gorkic

How to get lowest price for a ModelSim license?

Hi, We want to buy a ModelSim license. 1. Buy Xilinx-ModelSim version license from Xilinx website shop for $1150 with d...

25 comments posted 20yrs

posted by wtxwtx

25 comments posted 20yrs posted by wtxwtx

RocketIO AC coupling

Does anyone know whether the type of capacitor is important or not when AC coupling RIO signals to/from a VII-Pro pleas...

1 comments posted 20yrs

posted by enquiries

1 comments posted 20yrs posted by enquiries

xc3sprog -- any updates?

I was about to start hacking on xc3sprog after e-mailing the author and not hearing back, but I was curious if anyone e...

12 comments posted 20yrs

posted by jonas

12 comments posted 20yrs posted by jonas

How do I use the DDS core in a verilog flow?

I am new to using Xilinx cores. My intention is to use the DDS core, for which I was able to generate a number of files...

14 comments posted 20yrs

posted by barrinst

14 comments posted 20yrs posted by barrinst

Xilinx timing viloations

Hi all, I am facing timing violations in my FPGA with Max frequency 125 Mhz(Set up viloations). What are the steps to b...

7 comments posted 20yrs

posted by praveen.kantharajapura

7 comments posted 20yrs posted by praveen.kantharajapura

from VHDL to FPGA

Hi everyone, I'm a student electronics and computer engineering, and I've already got quite a bit of experience with ha...

6 comments posted 20yrs

posted by elesser

6 comments posted 20yrs posted by elesser

Xilinx ISE S/W Install kernel version "mismatch"

[crossposted because it's about Xilinx S/W, I'm running Slackware, and s.e.d is where all the really smart people hang...

14 comments posted 20yrs

posted by richgrise

14 comments posted 20yrs posted by richgrise

initialization sequence and auto refresh for sdr-sdram

Hi all, I have some basic doubts. The initialization sequence for sdram's from different chip manufacturers vary slight...

9 comments posted 20yrs

posted by subhasri.krishnan

9 comments posted 20yrs posted by subhasri.krishnan