Hi all!
I made a clocking module for Virtex4FX12 that accepts 66MHz from DCM0 (FX output at 6/9 ratio from 100MHz). Output is giving frequencies ranging from 35 to 66 MHz in 2MHz increments by changing Multiplier value (while D is fixed at 32) using DCM_ADV's Dynamic Reconfiguration (DRP). The output drives CMOS imaging chip MT9V403. The structure of this module is very simple and works perfectly in simulation and on oscilloscope, but I am not satisfied with the performance in real usage. When I change the clock settings the imaging chips fails to respond. The only setting that works perfectly is 66MHz (M=D=32). I also added BUFGCE at the output to enable clock only when DCM lock and syncronised to full clock pulse. That doesn't help either. Does anyone has the idea what can be wrong?
Thanks in advance
Guru