I have long been irritated that some of the tools in ISE are quite sluggish in Linux. For example, suppose I run a synthesis job in the background with a nice value of 19. In theory, I should barely notice that program (unless I run out of memory) if I'm looking at the current design in the floorplanner or whatever. Unfortunately, that is not the case. This is caused by the fact that the tools call sched_yield() very often. I have been aware of this for quite some time but never bothered to do something about it.
But it is actually quite simple to remedy this problem, just create a shared library containing a sched_yield that does nothing and use LD_PRELOAD to make sure that fpga_editor loads your shared library before libc is loaded. Now I can run fpga_editor with a synthesis in the background without any sluggishnes at all.
Of course, I cannot guarantee that this will work for you, but it seems to work just fine for me :)
/Andreas