Field-Programmable Gate Arrays

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Image rotation

Hello, I've come up with an issue, where I need to rotate the incoming video stream image by +/-5 degrees with 0.5 degr...
4 comments posted 11yrs
posted by mailsoc
4 comments posted 11yrs posted by mailsoc

Parallel execution of Systemc code

// Testbench rst=true; wait(10, SC_MS); rst=false; in1=8; in2=2; in3=3; in4=6; sel=2; wait(50, SC_MS); cout
9 comments posted 11yrs
posted by muyihwah
9 comments posted 11yrs posted by muyihwah

Prime number in verilog

Please any one give me the idea how i can generate prime number in verilog without the use of for loop. i computed in th...
6 comments posted 11yrs
posted by mawais2011
6 comments posted 11yrs posted by mawais2011

Monitor connections

Is there a way to monitor signals in existing wires? For example, with an oscilloscope and probe I can watch voltage ch...
7 comments posted 11yrs
posted by rick.c.hodgin
7 comments posted 11yrs posted by rick.c.hodgin

Using FPGA to feed 80386

Would it be possible to connect an FPGA up to an 80386 (or other) CPU, to respond to memory and port requests, and leve...
85 comments posted 11yrs
posted by rick.c.hodgin
85 comments posted 11yrs posted by rick.c.hodgin

Re: Problems with Xilinx SDK and LwIP

This is an old thread, but I had the same errors. Turns out I didn't have the hardware configured correctly. When I fin...
1 comments posted 11yrs
posted by josephbarrymore
1 comments posted 11yrs posted by josephbarrymore

VHDL Synchronization- two stage FF on all inputs?

Hello, I know this topic is beaten to death but I am a bit unlcear some things. I've recently encountered metastability...
38 comments posted 11yrs
posted by 91991
38 comments posted 11yrs posted by 91991

ICE40 Logic Cells

I was aware that the ICE40 devices have some limitations compared to other devices that are not so cost and power const...
2 comments posted 11yrs
posted by gnuarm
2 comments posted 11yrs posted by gnuarm

Which Altera to buy?

Greetings. I am new to FPGA programming. I am seeking to create a 40-bit 80386-like CPU core with a 32-bit and 64-bit F...
68 comments posted 11yrs
posted by rick.c.hodgin
68 comments posted 11yrs posted by rick.c.hodgin

FPGA on Android

- non-volatile FPGA plus FTDI USB chip - connects to an Android host mode USB port - application software in Lua, with...
0 comments posted 11yrs
posted by tim
0 comments posted 11yrs posted by tim

Low-end FPGA mezzanine standard

Anyone know if there's a standard(ish) for simple mezzanine cards for FPGA boards? I know about things like FMC and HSM...
21 comments posted 11yrs
posted by theom+news
21 comments posted 11yrs posted by theom+news

FYP Selection!

I have to choose a project for FYP from these three topics: I am confused b etween these three topics. My aim after Bac...
0 comments posted 11yrs
posted by awaish2011
0 comments posted 11yrs posted by awaish2011

IC40HX PLL Simulation

I'm trying to get started with a design using a Lattice ICE40HX (done that before) but this time I'm using the PLL. My...
0 comments posted 11yrs
posted by mk
0 comments posted 11yrs posted by mk

What would you say is the best board to buy

Im looking at a hardware project which will be a DVB-CSA descrambler. Idea is a pci-e board with an FPGA, any body know...
0 comments posted 11yrs
posted by joolzg
0 comments posted 11yrs posted by joolzg