Latest threads in Field-Programmable Gate Arrays

Name this pipelining technique

Hi, I vaguely recall reading papers that described an automated pipelining technique that could take an existing synchr...

4 11yrs

allanherriman

4 11yrs allanherriman

Timing Constraints: are there any "design patterns" indicating good practice?

I'll shortly be starting a design in a Zynq FPGA using Vivado. I'm confident that I will be able to use VHDL to create...

2 11yrs

spamjunk

2 11yrs spamjunk

Image rotation

Hello, I've come up with an issue, where I need to rotate the incoming video stream image by +/-5 degrees with 0.5 degr...

4 11yrs

mailsoc

4 11yrs mailsoc

Parallel execution of Systemc code

// Testbench rst=true; wait(10, SC_MS); rst=false; in1=8; in2=2; in3=3; in4=6; sel=2; wait(50, SC_MS); cout

9 11yrs

muyihwah

9 11yrs muyihwah

Prime number in verilog

Please any one give me the idea how i can generate prime number in verilog without the use of for loop. i computed in th...

6 11yrs

mawais2011

6 11yrs mawais2011

How to automatically allocate multiple bit fields into constant length registers?

Hi, I have to implement control interface in an FPGA connected to the bus with certain width of data bus (let's assume,...

12 11yrs

wzab01

12 11yrs wzab01

Monitor connections

Is there a way to monitor signals in existing wires? For example, with an oscilloscope and probe I can watch voltage ch...

7 11yrs

rick.c.hodgin

7 11yrs rick.c.hodgin

Using FPGA to feed 80386

Would it be possible to connect an FPGA up to an 80386 (or other) CPU, to respond to memory and port requests, and leve...

85 11yrs

rick.c.hodgin

85 11yrs rick.c.hodgin

Re: Problems with Xilinx SDK and LwIP

This is an old thread, but I had the same errors. Turns out I didn't have the hardware configured correctly. When I fin...

1 11yrs

josephbarrymore

1 11yrs josephbarrymore

VHDL Synchronization- two stage FF on all inputs?

Hello, I know this topic is beaten to death but I am a bit unlcear some things. I've recently encountered metastability...

38 11yrs

91991

38 11yrs 91991

ICE40 Logic Cells

I was aware that the ICE40 devices have some limitations compared to other devices that are not so cost and power const...

2 11yrs

gnuarm

2 11yrs gnuarm

Which Altera to buy?

Greetings. I am new to FPGA programming. I am seeking to create a 40-bit 80386-like CPU core with a 32-bit and 64-bit F...

68 11yrs

rick.c.hodgin

68 11yrs rick.c.hodgin

FPGA on Android

- non-volatile FPGA plus FTDI USB chip - connects to an Android host mode USB port - application software in Lua, with...

0 11yrs

tim

0 11yrs tim

Low-end FPGA mezzanine standard

Anyone know if there's a standard(ish) for simple mezzanine cards for FPGA boards? I know about things like FMC and HSM...

21 11yrs

theom+news

21 11yrs theom+news

FYP Selection!

I have to choose a project for FYP from these three topics: I am confused b etween these three topics. My aim after Bac...

0 11yrs

awaish2011

0 11yrs awaish2011

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