Field-Programmable Gate Arrays

  1. Home
  2. Field-Programmable Gate Arrays
15253 Threads Posts
to

Avnet Virtex-4 LX25 Evaluation Kit

Hello, Is thery anyone who has worked with Avnet Virtex-4 LX25 evaluation board. I am trying to communicate with the bo...
0 comments posted 19yrs
posted by jrabbani
0 comments posted 19yrs posted by jrabbani

Avnet Virtex-4 LX Evaluation Kit USB FX2 Issue

Hello, I have recently bought a Virtex-4 LX25 evaluation board from Avnet. It has Cypress FX2 chip for USB 2.0 communic...
2 comments posted 19yrs
posted by jrabbani
2 comments posted 19yrs posted by jrabbani

Mutiple MAC on OPB Bus

Hi, Is there any constraint regarding the number of Ethernet MAC that you can place on the OPB Bus? I have attempting t...
3 comments posted 19yrs
posted by get2venu
3 comments posted 19yrs posted by get2venu

CML output swing for V5

As per my understanding, Virtex5 GTP output supports CML standard. May I know the Common mode voltage and differential v...
4 comments posted 19yrs
posted by cpandya
4 comments posted 19yrs posted by cpandya

NIOS2 GNU tools under Windows Vista

Anyone have tried to run NIOS2 tools chain (especially gcc) under Windows Vista ? If I try I get the "fork_copy" error o...
0 comments posted 19yrs
posted by alessandro.strazzero
0 comments posted 19yrs posted by alessandro.strazzero

Unable to scan JTAG chain

I am using max 7000s series cpld.i am using altera byte blaster cable. i am getting error as "unable to scan device cha...
2 comments posted 19yrs
posted by kulkarku
2 comments posted 19yrs posted by kulkarku

how to delay a signal in virtex FPGA

Hi all, I've to delay a signal without using clock. So I want to use propagation time across logic functions like AND b...
12 comments posted 19yrs
posted by michel.talon
12 comments posted 19yrs posted by michel.talon

clock wide pulse transfer b/w clock domains

Hi, Please suggest me how to transfer a single clockwide pulse from high frequency clock domain and create a single clo...
13 comments posted 19yrs
posted by himassk
13 comments posted 19yrs posted by himassk

Global ressource problem

Hi i'm developping an architecture using Libero and Actel FPGA, i had a problem with global ressources, i had 8 global...
4 comments posted 19yrs
posted by Amine.Miled
4 comments posted 19yrs posted by Amine.Miled

SERDES question (Lattice ispHSI)

Hi! I need to design a simple serializer/deserializer as part of my bigger experimental project. I've started with read...
2 comments posted 19yrs
posted by czajnik
2 comments posted 19yrs posted by czajnik

Power Consumption near Timing Failure Point

I know that an FPGA's power consumption is basically linear with clock frequency, but does anybody know what happens wh...
12 comments posted 19yrs
posted by kevin_neilson
12 comments posted 19yrs posted by kevin_neilson