VHDL, how to convert sensor data to Q15

Sensor data length is 16 bit data, value is from -32768 to 32767,i think data format represented as one highest is sign and others are integers, who can help how to convert it to Q15 data format in VHDL?
Q15 like
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one sigh and others are fractional from -1 to 1
Sensor is ADC output is 16 bit format, one sign and other integer
so it need only divide ? ADC output to 32768 ??
Reply to
abirov
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OK. First, in an FPGA, if you're going to start with 16 bits and end up with 16 bits and divide by 32768, what do you need to do other than relabel the bits?
Second, review your number formats very carefully. I strongly suspect that everything is in 2's compliment where, indeed, the MSB is the sign bit, but things are more complicated than that. As far as I know, if it's called Q15, it's just 2's compliment integer shifted down by 15 bits.
Third, verify what the ADC is putting out. Some put out 2's compliment, some put out straight binary, and it's up to you to invert the first bit to get 2's compliment.
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Tim Wescott 
Control systems, embedded software and circuit design 
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Reply to
Tim Wescott
k
.
yes it is just a relabeling until you start multiplying.
1.15 * 1.15 results in 2.30 to get back to 1.15 you need skip an msb and us e the upper bits (and keep in mind the -1*-1 results in overflow)
-Lasse
Reply to
lasselangwadtchristensen
I wrote my own set of Q15 and Q31 code (software, not HDL) that travels around with me. Even though it takes a few clock ticks on every operation, I simply forbid 0x80..0 -- it makes life ever so much simpler.
Dunno how hard it'd be with an FPGA, but it might be worthwhile.
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Tim Wescott 
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Reply to
Tim Wescott
As others have indicated, there is no logic required to convert between the two formats. Here are some links for the proposed IEEE fixed point arithmetic package.
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Rick C
Reply to
rickman
And you might need this one too.
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Rick C
Reply to
rickman
..
Bit of extra info, I would not compile these packages yourself but use the ones supplied with your simulator as they are most likely tuned for some extra performance.
In Modelsim you can find the precompiled library in \floatfixlib and the source files in \vhdl_src\floatfixlib.
Good luck,
Hans
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Reply to
HT-Lab
It is too complicated to understand to me,I just want to divide range of nu mbers from -32767 to +32767 and get according data from -1 to +1. To get th is i must divide by 32767.
For this purpose i use Xilinx divider generator.So i use signed core, remin der type both fractional and reminder too.
It is OK when results must be 1 or more,but when it less then 1 thats sad. When result must be more then 1 quotient show right results in two's compli ment digits (according to datasheet) . But !!! fractional part is mad, cann ot use two's compliment digit conversion. when i divide any digit to 32767 (0111111111111111) and in fractional result is always dividend. I tryed fr actional part 32-bit width but no result/
Why it doesnot work ? Does anyone meet this problem ?
Reply to
abirov
Explain how it is "mad".
And please, please, please, stop for a moment and think on how sensible it is to use up a whole bunch of resources to do a divide by 32767 when a divide by 32768 is just a matter of shifting down by 16 bits -- which, on an FPGA, is simply a matter of relabeling your wires.
If you're absolutely bound and determined to divide by 32767, then use the following rule, which shouldn't take too much logic, because if you think about it you'll only be paying attention to the top two bits:
* If the input number has an absolute value less than 0x4000, shift down by 16
*
If the input number has an absolute value 0x4000 or greater, shift down by 16 and add (or subtract) 1 to (from) it, depending on whether it's positive or negative.
* Unless, of course, the input is 32767, in which case you need to shift down by 16 and _don't_ add 1, because if you do the result will be -1, which is a lot different from 1 - 1/32768.
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Tim Wescott 
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Reply to
Tim Wescott
Shifting down by 15 means what? My english very poor sorry. You mean shifting down like following vhdl code :
Ding(15) is sign bit. Dout
Reply to
abirov
I got it, and finish this problem, Very thanx everything is OK now.
Reply to
abirov
> Shifting down by 15 means what? My english very poor sorry. > You mean shifting down like following vhdl code : > > Ding(15) is sign bit. > Dout
Reply to
rickman
That's what I said! Only Rick's version makes sense.
Yes -- perform a right shift. Except, as Rick says, you're not really moving anything, you're just re-labeling the wires. Your 16-bit integer had a wire with weight 1, a wire with weight 2, etc., all the way up to a wire with weight 32768. You "shift" that by relabeling your wires as having weight 1/32768, 1/16384, ... 1/2, 1.
Note that there is no physical operation whatsoever inside your chip to perform this shift -- you're just _thinking differently_ about the number for all operations except multiplications.
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Tim Wescott 
Wescott Design Services 
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Reply to
Tim Wescott
The bundle of wires doesn't care whether you think it has a decimal point in it or not.
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Rob Gaddi, Highland Technology -- www.highlandtechnology.com 
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Rob Gaddi

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