Quartus, building "Safe" FMSs

This has been discussed at great length on comp.lang.vhdl:

There's no simple answer. Consider using the binary (minimal bits) setting and see what you get.

-- Mike Treseler

Mike,

Thanks. I will read the thread. It always seems to be a problem when I try a new tool. And your right, it is not a simple problem when the people developing the tools have not considered the problem. I would have thought the Quartus tool would have had this covered. I like using the Synplify tools for this reason.

I had reposted the question to Altera last week but have yet to hear a responce. If anything comes of it I will post.

Synplify has two different "safe" modes.

One is to prevent sequential optimizations on the state register. You do this with the syn_preserve attribute on the register (not the best name - I know). Most synthesis tools have some way to do this.

The second is to let Synplify extract the state machine and to specify a syn_encoding attribute of "safe,onehot" or "safe,sequential" on the state register. In this case Synplify automatically builds an extra reset condition based on a pipelined detection of an illegal state. By separating the illegal state detection logic and giving ourselves more time to detect the illegal states we can make a more area efficient recovery circuit and a faster FSM. This feature is covered by a patent so you probably won't see it in other tools.

- Ken McElva>>This has been discussed at great length on comp.lang.vhdl: