XilinX MAC FIR

Hi,

A MAC FIR is not ideally suited to your application, given those parameters. At a clock rate of (say) 210MHz, you would need 32 parallel MAC units to keep up with the data input rate. This is virtually a full-parallel FIR implementation. Of course your achievable clock rate will depend on what part you are targeting.

You should probably still be able to use the Xilinx core, as it is capable of using multiple MAC units according to your data rate requirements. Provided that you configure the core such that it has enough processing power to keep up, the handshaking on the data input samples will cause you no problems.

Cheers,

-Ben-

You can do this very easily for the cost of $595 US. Just buy a Xilinx ML-403 board, and a couple of 32x3 .100" connectors to get the data in and out of the board. The XC4VSX35 fpga on the card has 192 hardware multipliers and adders, arranged in 2 columns of 96 each. One column should suffice for your requirements, and it will run as a 96 tap FIR filter at 400 MHz. Getting data in & out at 400 MHz would probably require using LVDS, but 105 MHz should be relatively easy using CMOS 3.3V or other single ended signaling. You'll probably spend more time getting the IO timing right than on the FIR filter, which can be generated as a monolithic core by the Coregen tool. You really don't want to use the MAC FIR, by the way. Just a standard FIR will work fine.

John

The ISE 7.1 coregen

Ben, John

Thank you for your replies

John, I think, as you said, MAC FIR is not relally suited for m

application. And since I have an XC2VP30, the best is to manuall program a FIR filter by myself. I think it's could be not to difficult

Ben, I agree with you (a s I said above). Concerning the hadrwar

Platform, it's an ADM-XPL board o Alpha-Data with a XC2VP30-5

Thank yo