CMOS Image sensor & Two-wire serial interface

Nov 26, 2008 9 Replies

Hi, I tried to look for similar topics in the archive but no luck.



I have a cmos image sensor, and it has a "two-wire serial interface" to read/write its on-chip registers. I tried to treat it like a I2C protocol, and fed a 100KHz at SCL, and write an address byte at SDA, but cannot get the acknowledge bit.



Is it about the values of pull-up resistors in SCL and SDA? Or the clocking frequency problem??



Thanks.



Kcin


yes. Or it might be something else. What does the data sheet tell you?

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It's a Micron's CMOS image sensor. The spec only describes both SCL and SDA should be pull up 3.3V with a 1.5k ohm resistors. No suggested clock rate of SCL. It does not have any signs of the word "i2c" as well, it calls it "Two-Wire Serial Interface". What standard is it really?

"Serial Bus Description Registers are written to and read from the MT9T001 through the two- wire serial interface bus. The MT9T001 is a two-wire serial interface slave and is controlled by the two-wire serial clock (SCLK), which is driven by the two-wire serial interface master. Data is transferred into and out through the MT9T001 through the two-wire serial interface data (SDATA) line. The SDATA line is pulled up to 3.3V off-chip by a 1.5K=D9 resistor. Either the slave or master device can pull the SDATA line down--the two-wire serial interface protocol determines which device is allowed to pull the SDATA line down at any given time."

I2C interfaces often aren't called I2C, presumably due to possible licensing/patent issues or subtle implementration differences. However the required waveforms will be in the datasheet.

you need to get the full data sheet. Omnivision made us sign a NDA. Micron (Aptina) might require it too. Contact Aptina or their distributor if you have to. Bob

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According to the datasheet at

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"The two-wire serial bus operation requires certain minimum master clock cycles between transitions. These are specified in the following diagrams in master clock cycles."...

and then there are a bunch of timing diagrams to peruse.

I am actually working on the same thing and can not get an acknowledge either.

I am running from the LH a SCL of 100KHz and my PIXCLOCK (which is the master for the MT9T001) at ~ 2.5 MHz.

For some reason I still cannot get an acknowledge bit on I2C.

I checked the timing diagrams and a 2.5MHz clock should meet the minimum by far, but still nothing...

Anybody got any ideas?

--Daniel

I tried to feed 100KHz and 400KHz to SCL @ 48MHz master clock, but still no ack bit.

I will try to lower SCL to 80KHz.

More, I am wondering if SCL depends on the master clock.

I read several specs and it seems that many of their cmos run with this "2-wire serial interface". What is the trick really?

Thanks.

Kicn

k

ms

Did anyone ever resolve this issue. I am trying to write to a similir image sensor and not receiving the ACK. I am using a bit bang I2C implementation. I have reviewed the image sensor timings and I am well within spec.

Thanks, Elliott

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Which timings have you checked? Video or I2C?

I would actually suggesting capturing your I2C communications on a digital scope and checking what is happening and that your are sending the right information.

Often these sorts of problems end up as

Incorrect bit pattern (address/data) Incorrect waiting for bit times incorrect or open connections incorrect voltage levels used incorrect I2C termination incorrect oscillator on imager Some other configuration on the imager missing/wrong

It is very, very rarely the device at fault, sometimes the documentation.

Paul Carpenter | paul@pcserviceselectronics.co.uk PC Services Timing Diagram Font GNU H8 - compiler & Renesas H8/H8S/H8 Tiny For those web sites you hate

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