I've attempting to select an FPGA for a new design.
The design will have 9 of the following: 12 bit latches 12 bit down counter 1 bit output latch
So one measure of the size might be 25 registers * 9 = 225 registers.
The counting freq is 15 MHz.
The latches get loaded from an existing micro. So I need a 12 input pins for a data buss, 4 input pins for which register, a clock pin and let's say 4 pins for control lines. Along with the 9 output signals.
So another measure is 12+4+1+4+9 = 30 pins not counting power and ground.
It would also be desirable to be packaged in a PLCC but TQFP in ok.
And the device should be reprogrammable using JTAG (add 4 more pins).
Voltage is not much of an issue. However 5 V tolerant I/O would be nice.
I've looked at Lattice and Altera and haven't found the perfect solution. I can use larger than necessary Altera devices (ACEX1K) but that seems to be the wrong direction.