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Eighty layers of metal!

Article intended for FPGA-types has a nice summary (for dummies like me) of the state of the wire-delay/interconnect problem:

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"James Meindl at the Georgia Institute of Technology, who has become an expert in predicting the impending impact of physical parameters on future IC generations, has taken on the interconnect problem. His analysis predicts 80 levels of metal by 2014 if no architectural changes are made in circuit design."

Won't happen of course. Possible solutions: get away from Manhattan routing (25% savings in wire delay--yawn), copper interconnect (been done of course, discovered from the same article that copper atoms like to diffuse into silicon, maybe it's just as well that chips become obsolete every few years), repeaters every few atoms or so (why do we keep trying to do it with electrons? Because we're *electrical* engineers, that's why), and then

"Another possibility in this direction is the introduction of photonic waveguides for long interconnect lines. There is some hope here. With recent work on building photonic bandgap structures into silicon circuits, this might become a practical option for designers. Photonic structures can now be defined on-chip with the same lithographic processes used in CMOS manufacturing. Photonic interconnects do not carry the RC delay penalty that creates so many problems for wire inter connects."

RM

Reply to
Robert Myers
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One thing I've never understood is what makes IC P&R different to PCBs? PCB autorouters have been doing 45 degree routing for years... Interested minds want to know.

Cheers!

Martin

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Reply to
Martin Thompson

It is, apparently, common knowledge that copper is doom, in terms of silicon. So I asked my chip-process-engineer brother how Intel and IBM can be investigating the use of copper. My digest of his answer is that the "copper equals doom" theory appears to be bunk. It certainly has some ways to go wrong, but from a chemistry and solid-state physics standpoint, it ought to be able to work.

I may have misinterpreted what he said, but I throw this into the mix for discussion purposes. :-)

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Reply to
Chris Torek

Hi Chris,

Copper has been solved by the process guys. The trick is that you have to put a barrier metal (tantalum?) between the copper and the silicon dioxide/FSG in order to prevent the copper from diffusing into the dielectric. This makes copper processes more complicated (dual damascene) and hence a little more costly, have higher defect rates (tantalum bridging, via underfill, etc.) Apparently, things get trickier when you mix copper with lower-k dielectrics.

There's a nice little paper here that describes things at a pretty high level:

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It took a while for the fab guys to get everything worked out, but now adays I think almost everyone's in copper at .13u and definitely below. We've been successfully manufacturing and yielding chips use copper interconnects since the 0.15u node (in 2001), and all of our recent FPGAs use an all-copper process (APEX 20KC, APEX II, Stratix, Stratix GX, Cyclone).

Regards,

Paul Leventis Altera Corp.

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Reply to
Paul Leventis

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gives an overview of barriers used. Tantalum Nitride is one of them, you also can use Titanium or Tungsten Nitride, and optionally add Silicon. Basically what you want is a robust crystal that doesn't allow the copper to migrate through. There are many available, pick those which can be processed easily and don't cost too much. Titanium Nitride is already used as barrier for the AlCu alloys, so the question is whether it's good enough (there are doubts). Tungsten has the disadvantage of crystalizing into nano-needles, which increases the surface resistance (not that Tungsten has a good inner resistance, either), but it works. Tungsten is also often used as local interconnect, and some processes use Tungsten barriers for AlCu (e.g. xfab 0.6u).

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Bernd Paysan
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Reply to
Bernd Paysan

In article , Chris Torek writes: |> In article , |> Robert Myers wrote: |> >Won't happen of course. Possible solutions: get away from Manhattan |> >routing (25% savings in wire delay--yawn), copper interconnect (been |> >done of course, discovered from the same article that copper atoms |> >like to diffuse into silicon, maybe it's just as well that chips |> >become obsolete every few years) ... |> |> It is, apparently, common knowledge that copper is doom, in terms |> of silicon. So I asked my chip-process-engineer brother how Intel |> and IBM can be investigating the use of copper. My digest of his |> answer is that the "copper equals doom" theory appears to be bunk. |> It certainly has some ways to go wrong, but from a chemistry and |> solid-state physics standpoint, it ought to be able to work. |> |> I may have misinterpreted what he said, but I throw this into the |> mix for discussion purposes. :-) |> --

Copper is doom. IBM shipping large quantities of copper metallized chips. Hmm, secret double damascene process to keep copper out of si.

Change "it ought to be able to work" to "It works"

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Del Cecchi

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