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DDS sort of related thing

We're designing an 8-channel waveform playback box for a aerospace customer. They will load large waveform files into our box, and we'll play them, each at his programmed clock rate.

I call it the Wayback Machine, and included this figure in the proposal:

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One issue is that he may want "gear ratio" frequencies. If we use a binary-radix DDS to clock the output DAC, the frequencies are goofy and it's hard for him to get exact integer ratios.

Another thing that we want to do is smooth his waveform steps. The playback clock rate can vary from low Hz up to 400 KHz, and it's clumsy to switch in various lowpass filters as a function of that rate.

Here's the binary-radix version:

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We clock the FIFO every time the phase accumulator rolls over.

The high N bits of the phase accumulator (16 or 18 maybe, to match the FPGA multiplier width) are used to linear interpolate between samples, always at 2 MHz. The output lowpass filter can now be fixed at something like 500 KHz.

I declared that the customer frequencies all be quantized to 0.001 Hz exactly. That lets him specify frequency gear ratios without slow channel-channel phase creep from binary rounding. So we came up with this:

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The trick is to scale up the N MSBs of the mod-2e9 phase accumulator to generate the X and 1-X interpolation factors. That's a multiply by

2^31/2e9, which is about 1.073 (not 1.05... sorry) which is easily done. The N MSBs essentially scan the range 0 to 0.9313 fractional, so we have to stretch them up to 0.9999.

Higher-order interpolations are possible with three samples, approaching a spline curve or bessel filter, or something, but I think the linear interpolation will look great on a scope, as compared to raw stairsteps.

The decimal frequency quantization thing could be done in a binary DDS with a goofy clock frequency, but that has undesirable side effects here. Or a really wide DDS could express 1 mHz pretty closely, but not exactly, and we could always load Fset with a multiple of that. Again, we have system reasons to not do that.

It's fun to bat this sort of stuff around.

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John Larkin         Highland Technology, Inc 
picosecond timing   laser drivers and controllers 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin
Loading thread data ...

You don't pay much attention to the stuff that gets posted here, do you.

This has come up in Phil Hobbs' "DDS Wisdom" thread, and you got it wrong there too.

You can buy Analog Devices DDS chips which don't limit you to a binary radix. Here's one

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On page 14 of the data sheet there's discussion of the "programmable modulus mode", which seems to solve your (technical) problem.

Nice idea. It won't work as easily with a non-binary radix. You'd need a pair of real binary multipliers to calculate a pair of non-binary fractions, which is easy enough, but might take up a bit real estate inside the FPGA.

And useful, when you have been wasting time solving a non-problem arising in something you know that ain't so.

--
Bill Sloman, Sydney
Reply to
Bill Sloman

It's WABAC, colloquially "Wayback" -- which is probably what the Brits call "The Drive Home" (Wayout == Exit) :>

Reply to
Don Y

Why are there so many small towns in Britain named Loose Chippings?

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John Larkin         Highland Technology, Inc 
picosecond timing   laser drivers and controllers 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

Perhaps their version of "Springfield"?

Reply to
Don Y

call

It's an old joke. "Loose chippings" is a warning sign left at the side of r oad when the U.K. road-menders have filled in pot-holes with gravel/"stone chippings", and not bothered to bind the loose rocks together with tar. Sin ce there is a UK town called "Chipping Norton"

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where "chipping" was just the old-English for "market" you can see how it w orks.

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Bill Sloman, Sydney
Reply to
Bill Sloman

And Chipping Sodbury :)

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Reply to
TTman

I did something similar in a DDS and used a mixed radix accumulator. This gets rid of the awkward multiply by 1.0xxx. You want the lsb of the step size to be 1 mHz, so the lower part should be counting by 10000 and the upper 18 bits counts binary. The clock rate needs to be 2.62144 MHz and your setup software will need to perform the appropriate conversion to the step size when writing to the register. Resolution to

1 mHz and no correction multiply needed for the linear interpolation. It's nice to get rid of the approximation.

In my case it was because I had an awkward clock rate of 24.576 MHz (audio sample rate clock). I had to incorporate a 3 in the modulus along with some decimal ratios, etc.... Looks ugly on paper but it works great. The linear interpolation multiplies were all binary and the upper and lower portions of the phase accumulator were as needed to make it all come out right. I was working in a part with no multipliers so this was important.

--

Rick
Reply to
rickman

peabody_and_sherman.jpg

Wayback_Binary.JPG

Wayback_Decimal.JPG

There are better ways of doing polyphase filtering than simple linear interpolation.

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www.wescottdesign.com
Reply to
Tim Wescott

:
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this might be interesting:

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-Lasse

Reply to
Lasse Langwadt Christensen

Really?

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John Larkin         Highland Technology, Inc 
picosecond timing   laser drivers and controllers 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

That is nice. Someone obviously spent a lot of time on the math there.

We've done a bunch of DDSs in Xilinx and Altera FPGAs, usually the simple way: binary phase accumulator and sine lookup table, without the higher-order tweaks. We do sometimes add a phase rotator between the phase accumulator and the sine LUT, so our customers can play with the phases of clustered channels.

At high frequencies, we generally get most harmonic distortion from the DAC and downstream amplifiers, not from the DDS math. Close-in spurs are still mostly DDS math things.

Our current app, playing waveform files, is not exactly DDS, so the Xilinx trig tweaks don't apply. I have no doubt that the s/n dominant will be the quality of the customer's data, in the waveform files they will be acquiring and then loading into our box for playback.

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John Larkin         Highland Technology, Inc 
picosecond timing   laser drivers and controllers 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

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you don't use the xilinx core?

-Lasse

Reply to
Lasse Langwadt Christensen

Haven't so far. A basic DDS is bog simple, and we often add tweaks like phase rotation, amplitude scaling, DC offset. Some of our gadgets allow one DDS to generate the frequency, phase, or amplitude of a second DDS, to make complex modulations. That's easier to do ourselves.

We are probably giving up a few dB of purity by not absolutely optimizing the roundings and sine LUT values, but our customers are in the waveform generation/physical system simulation business, not the RF business, so it's OK.

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John Larkin         Highland Technology, Inc 
picosecond timing   laser drivers and controllers 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

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scaling and offsets is not really part of the DDS, that's stuff bolted on to the output.

The core just need clk, rst, phase offset and increment so it can do anythi ng a diy DDS can, but it'll be smaller faster and verified

-Lasse

Reply to
Lasse Langwadt Christensen

We have been doing our own DDS logic since before any of the FPGA people were providing DDS IP. Don't know why their block will be any smaller or faster, or why that would matter.

As far as "verified" goes, I personally dislike opaque black boxes inside of FPGAs. Does the Xilinx thing generate visible VHDL, or is it some encrypted block?

We're engineers. We design things!

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John Larkin         Highland Technology, Inc 
picosecond timing   laser drivers and controllers 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin

Cool! (have last 2 URLs the same..)

Reply to
Robert Baer

I do hope you're being sarcastic. If not:

Yes. Thinking that linear interpolation is the beginning and end of polyphase filtering shows the same level of sophistication as a guy who understands that he needs a base resistor on his 2N2222, but doesn't quite grasp the need for the diode across the relay coil.

Try Googling "Polyphase Filter". Also Google "Secret Rabbit Code" (SRC = "sample rate converter") for a well fleshed out example in C.

For what you're doing, cubic interpolation or splines may be the best, as you're probably more interested in reducing the time-domain error rather than any frequency-domain nastiness.

--
www.wescottdesign.com
Reply to
Tim Wescott

2N2222? Do they still make those? 
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John Larkin         Highland Technology, Inc 
picosecond timing   laser drivers and controllers 

jlarkin att highlandtechnology dott com 
http://www.highlandtechnology.com
Reply to
John Larkin 

--
www.wescottdesign.com
Reply to
Tim Wescott

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