I can see the rationale for that use case.
I appreciate the desire for this in a future VHDL.
Meanwhile, this is a good place for a function.
It can be declared locally, but my solution is to treat bar_record_t as an abstract type. Wrap it in a package along with functions to manipulate it.
package bar_type is type bar_record_t is... function validate (B : bar_record_t; V : bar_valid_t) return bar_record_t; ... end bar_type;
-- in the package body function validate (B : bar_record_t; V : bar_valid_t) return bar_record_t is variable temp: bar_record_t := B; begin temp.valid := V; return temp; end validate;
Then the main code simply reads:
bar0