Where are the LCD or OLED bitmapped displays?

They're sending us a sample of part number NHD-0220AU-FSW-FTS, 2x20 with white backlight, around $7. Should be here soon. I'll let you know how it looks.

There are tons of 2x16 and 2x20, 33 mm high backlit displays around. We picked this 30 mm unit because we're squeezed on height.

John

The Newhaven people claim they'll do custom glass for about $1000 NRE.

John

Dammit Eric, I nearly choked to death on my drink :-)

G.

I've also seen this often in multi-bit DDS's, where both phase and amplitude truncation/quantization cause close in spurs that are troublesome, especially if the DDS output is being heavily multiplied ( e.g. when used as a PLL reference with big N. )

Since that lengthy 2002-vintage synthesizer thread where I attempted to describe this [1], I have put together some more detailed plots showing the spurs collapsing in on the carrier near a 'bad' tune word [2]; as further explained in a couple of associated posts [3], these plots just model the numerical artifacts, not any analog harmonic aliases or nonlinearities.

Brian

[1] close in DDS phase noise artifacts: [2] plots of DDS spur pileups ( modeling numeical spurs only ) [3] related posts about the pdf file in [2]

Thanks for this link, this was an interesting discussion. I really like the idea using a DAC for creating a sine output and a comparator for creating a square wave, because then you are using more bits of the accumulator and you can avoid wandering, if you want to generate 1.000....0001 * fclock.

I think this could be implemented with low bit counts for the DAC, if you feed it to a good analog band pass filter and if you use very good comparators for low jitter. And it should be possible to use a fixed filter and then feed it back into a PLL for producing a wide range of output frequencies.

For very high precision you could use a VCXO to synchronize the reference clock to GPS or easier to use time bases, like DCF77 in Germany or one of the other many time and frequency stations in other countries:

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Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

Using a DAC with hard limiting will reduce their level vs. a single bit DDS, but the bothersome truncation/quantization artifacts are still there in a conventional DDS.

Veering back onto discussing single bit DDS's, given a high rate serializer to press into use, there are a variety of fractional-N or noise shaping techniques that should work well, e.g. [4],[5]

Brian

[4] HP single-bit fractional-N: "A Multiple Modulator Fractional Divider", Miller/Conley, 1990 (also reprinted in Kroupa's DDFS book)

[5] bandpass delta-sigma modulator:

I'm not sure, if this results in a cleaner frequency output, because it has other artifacts.

For a test equipment signal generator, which needs to change the frequency only every some seconds, maybe an easier idea could work: Using a VCO, controlled with a high precision 24 bit DAC (like one of these high quality audio codecs, which are nevertheless cheap, because of mass production). The frequency of the VCO could be measured by the FPGA over a long time, maybe counting the cycles in one second, and sophisticated (filtering, PID etc.) adjustments for the VCO voltage can be implemented. The only drawback is, that the VCO frequency and the DAC voltage must be very solid for at least some seconds, which means good decoupling and filtering of the power supply, maybe shielding etc.

--
Frank Buss, fb@frank-buss.de
http://www.frank-buss.de, http://www.it4-systems.de

We just got the demo Newhaven 20x2, 30 mm high COG white backlit LCD. It's all glass, no PCB, so it would be mounted by soldering the leads, plus some adhesive or foam tape to a motherboard. Visually, it's gorgeous. $7.07 single-piece price!

ftp://66.117.156.8/Lcd_front.JPG

ftp://66.117.156.8/Lcd_back.jpg

ftp://66.117.156.8/Lcd_demo_bd.JPG

John

Now that is neat! Is it ROHS? Website?

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EB

You have seen these ?

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Regards,

Adrian Jansen           adrianjansen at internode dot on dot net
Design Engineer         J & K Micro Systems
Microcomputer solutions for industrial control
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Suppose I had a collection of input clocks I could pick from.

How many would I need and/or what frequency pattern would I pick in order to avoid the nasty cases?

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It depends on what you think is nasty. What's your PLL loop bandwidth and what's an acceptable level of jitter? What's your desired range of output frequency coverage?

Subharmonics - where Fsys is approximately N*Fout - are the worst points. If those were all that you needed, you'd have to make sure you can cover the subharmonics for one Fsys with another crystal's selection far enough from its subharmonics that the combination works.

DDS frequencies are effectively a cascade of m/m+1 style dividers where the +0/+1 selection is fed by the downstream dividers which chops up the Fsys/m_ish subharmonic. Each effective divider stage reduces the maximum jitter amplitude by a factor of about m. If you have several dividers, the amplitude of any close-in phase-noise spur will be small. The situations that are close to the highest frequency subharmonics have a first-stage divider with a small m and a second divider with a very large divide factor, supplying the m/m+1 change very rarely such that that 1/m unit interval phase step is followed very dutifully by the cleanup PLL and not filtered out. Two small divider stages can still give you a large enough remaining jitter value that the close-in condition still needs to be covered by another crystal.

Now. If you have multiple crystals, the frequency differences will come into play. If you want to choose the crystals so that the "bad" frequency windows don't overlap, the system must be designed so the bad windows *with tolerance* don't overlap. Add to that the complexity that you'd have to use one crystal as a "master" frequency to monitor and adjust the sub-Hz frequency value of the other crystal (to avoid a 12 ppm jump when changing from 1201001 Hz to 1201002 Hz, for instance) and you have an ugly situation.

Your requirements will help drive the system. I'd do many things before I went for multiple reference clocks, personally.

- John_H