Virtex4 : speed improvement

generation (and nearest competing FPGA as well? ;-))

V4-10? and what about -11 or latest -12 speed grades? any figure?

Steven,

Are you planning to use any of the new features, or re-targeting anything?

If so, there will be speed improvements.

If you just take the V2P design in -7 (fastest speed grade) and retarget for V4-10 (slowest speed grade), you may come out on par.

But, the ISE software also has improvements, so a design done a year ago will be able to run faster if re-run today, just from improvements in the tools.

Comparing the fastest speed grade of the previous product, to the slowest speed grade of the new product is likely to not show much of an improvement. Especially since the variation in speed as we shrink gets wider (speed grades offer more improvement).

Austin

Howdy Steven,

We've been looking at exactly that for a few of our designs. The answer is that it depends. If you study the timing specs in the latest datasheets, (sometimes with the aid of 6.3.3i speedprint), here's what you'll find:

The core of the V4 looks to be somewhat faster, but setup and hold times into some elements have increased slightly over V2Pro, and unregistered clock-to-out times from memories (LUT or BRAM) are _slower_ than the V2Pro-5. Call it the triple-oxide effect? If you can afford to register your BRAM outputs, you can get the blindingly fast access (which is what their marketing department advertises). Global clock nets have considerably more delay as well (unless you use a DCM) - if you need low prop delay clock lines without a DCM, you must use regional clocks (which are a piece of cake now, although it sure seems like there are fewer total local clock resources now).

I would highly recommend studying your top couple critical paths and compare the timing changes between the families to verify these differences won't adversely affect you. Or better yet, retarget the design to V4 and get the complete picture.

Have fun,

Marc