Virtex4 CLKX2 DCM Jitter

Absolutlely. But the anti-resonance peaks will be much lower. Done properly, the impedance peaks stay below the minimum design impedance.

I look forward to checking out your data when I have a moment.

Hi Gerhard, Thanks for posting that. A very interesting series of experiments. They show how both form factor and layout are important. I wonder if you saw the thread back in March about X2Y caps? Subject, "Bypass caps, X2Y and 'puddles'". You may like to check it out, there are links to some similar experiments there also.

FWIW, I think all this different value caps thing is bunkum. Especially if they're in the same sized package. Unless someone does a detailed 3-D analysis _INCLUDING_ the bond wire, the BGA pacakge traces and the BGA balls, I won't be convinced by 'resonance' bluster. OTOH, the X2Y stuff has me convinced that I should think even harder about bypass networks in my next design. Thanks, Syms. p.s. I guess it would be fairly straightforward for Mike (the OP) to change some values in his bypass network and see how it affects jitter. That'd be interesting.

Yeah, I saw that too. I think a passive filter will perform better than the suggested circuit above a few hundred kHz. The linear regulator solution runs out of bandwidth. HTH, Syms.

That file will grow, I'll test X2Y when I get my next board fabricated. On 1.5 mm epoxy they would probably be pearls before swine.

Gerhard

That should suit most of us on this newsgroup then... :-)

I'm looking forward to seeing your results!

Thanks, Syms.

Symon,

I have one ppt slide, but I can't post it here.

If you email me directly, I will mail the slide to you.

Austin

Yes, that is the plan.

Xilinx are looking at my layout, and I will incorporate their feedback and some other tweaks into a respin. I will get these boards manufactured with a few different mixes of caps around the Xilinx and spend some happy days in the lab. This won't happen for a couple of weeks of course.

The design has approx 72 outputs wiggling at 400MBits and 76 outputs at

By overriding the auto-IDELAY calibration and doing a slow manual scan through the taps while this memory self test is running I can get a feeling for my margin, and I get zero errors over about a 0.5UI range which is pretty good.

I would like to get my ~500pS jitter loss back of course (if I run the self test in super slow motion, the eye is a few taps wider so the increased jitter is hurting me slightly)

Regards, Mike.

Mike,

Wow. 0.5UI is a lot of margin. It really is.

And, yes, I think we can recover some more "eye" for you, and increase your margin further.

I suppose since no one has emailed me for the "bad" anti-resonant powerpoint slide, we don't have any "unbelievers" here.

Fact is, doing a sweep of IO switching over frequency will show if there are any "really bad" places in your power distribution network (vs frequency).

Doing a network analysis (using a variable frequency RLC meter, or a VNA

-- although a VNA is not very good at milli-ohm impedances), will confirm that at some frequencies, the bypassing is all but non-existent.

Austin

I'm a believer *and* I'd like to see the slides but I figure it would be more useful in an application note than as a stand-alone slide that I'd lose on my hard drive somewhere. I'd love to see proper power-distribution design used more widely.

My recall of QDR is a little fuzzy- do your address outputs also use the FPGA DDR output registers, or is only the clock/data done on both edges with a DDR flop?

Is this all done with global clocks, or are you using regional/local clocks?

If this were V2, I'd ask if you were using internal DDR clock inversion for the DDR 180 degree clock phase, or using two BUFGs to distribute clock and NOT clock.

I like to have some LVDS I/O available for these sorts of measurements; I've been thinking about plunking a vertical launch SATA connector down on my boards to provide an easy clock test I/O connector ( less space then 4 SMAs, easier to probe/drive than resistor pads )

Brian

Address change at SDR rate but I am still using DDR output flops.

Global clocks in V4.

thankfully we don't have to do that anymore :)

neat idea that! /Mike