Virtex 4 desing : ChipScope insertion impacts my timing problem debug

Hi, I am working on a Virtex4 FX design, when the system clock runs at

100MHz, the memory controller core does not work correctly. Then I inserted ChipScope trying to identify the problem, but once it is inserted, the problem is gone!

I know it is of timing problem since if I lower the system clock to

50MHz, there is no problem either.

It looks like that after the chipscope is inserted, somehow the routing is altered in favor of the memory controller.

I just wonder if there are any trick so that Chipscope insertion does not impact design routing?

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Generally the answer is that Chipscope always has some effect. However you can minimise the effect by pre-registering signals used as inputs to chipscope. This reduces the raw fight for resources between where design elements need to be and where Chipscope needs to be with the chip.

The problem you describe does sound like timing. Have you set proper timing constraints? Have you considered the implementation where any clock boundaries that are crossed?

John Adair Enterpoint Ltd. - Home of MIN-CAN. The Spartan-3 CAn Bus Development Board.

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John Adair

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