mosfet analog mux, RC timeconstants

Aha, some nice DMOS mosfets springing from the mold of the venerable sd210 - sd214 series. The sd5000 series is a set of popular parts made by several manufacturers, featuring small FETs with high speed (600ps), low Ron (30 ohms at 10V) and moderate capacitance (2.4pF). I've used the sd210 and its siblings for 20+ years, and am a big fan, but I've yet to use any of the sd5000 monolithic multiple-FET family.

Well, well, well. You've fixated on the MOSFET's 50-ohm resistance, and have ignored the all-important world of charge and capacitance. For example, when you apply a gate pulse, what do you think happens to the FET's other pins? You force a voltage swing on the gate and this is transferred directly to the other pins via the FET's internal charge-storage capacitances. Your output node is a tiny 2pF and 10M, well-suited to respond to such a large capacitively-induced stimuli.

Second, you haven't told us much about your 83-kHz 10V gate signals; they aren't on your waveform pics. What's the story there?

However, the sd5401 should have a < 50 Ohm resistance with Vgs= 5V, and I keep my Vgs to >= 7V, so if I'm charging a 2pF capacitance through a 50 Ohm (mosfet) resistance, that should be a 1ns timeconstant, if my understanding is correct. Doubling the capacitance should double the time constant (T=RC), but when I tried this, the edge only increased to 400ns.

As Win said, you focused on Rds(on). Looking at the datasheet, we see:

Drain node capacitance ~ 3pF Source node capacitance ~ 5pF

Gate node capacitance ~ 3.5pF

In addition to the gate charge step (which will be small but will still exist) at the Vgs threshold, these capacitances are larger than your load. The 10M resistor will also have significant (in this case) capacitance, which could easily be larger than the load in it's own right. What model did you use for it?

Datasheet at:

Those extra capacitances are definitely going to spike your plans in this case.

I''ll second the motion for details of the gate drive waveform

Cheers

PeteS

I think I see part of what you mean - there is a timeconstant associated with charging the gate up to Vt, given be the output impedance of the device charging the mosfet gate, and the mosfet Cgs+Cgd+Cgb capacitances. This is very small though and only part of the problem. In reference to PeteS's post below, I don't quite understand why it matters that the mosfet parasitic capacitances are greater than my load capacitance -- why does this significantly affect the speed of my output signal?

For my spice sims I've been driving the gate directly with some ideal PULSE() voltage sources - 5ns edges at 830kHz. In the following plot, V(1) does goes up to 10V, but the picture seems to keep clipping when I convert to png for some reason:

However, for my implementation I'll be using an FPGA to generate the squarewave gate control signals, so the circuit might look something like this:

I tried simulating this and I get the results shown in the following:

(again more clipping of the upper plots). The first plot shows the two out-of-phase 5V gate control signal from the FPGA, the second plot shows the two out-of-phase and inverted 10V analog-mux gate control signals, and the final plot shows the analog signal inputs and output.

Cheers,

Steve

Whoa! You're using 825-ohm gate resistors and expect ns time-scale switching? You don't need to add any gate resistor. And 550k pullup resistors, what's the deal? You know better than that!

The 825 ohm gate resistor was just a calculation based on a maximum output current of 6mA at 5V.

As for the 550k pullups, that's again because the mosfets weren't behaving as I was expecting. For the next bit, I've slowed down everything by a factor of 1000 so that I can hopefully ignore the high frequency problems, so the inverter is now controlled by a 830Hz, 0-5V square-wave with 5us edges.

If using a 4k7 pullup to a 10V supply, then when the gate-source potential is high (5V), the mosfet should have a resistance of 50 Ohm, and the output should be 10*50/(50+4k7)=0.1V. When the gate-source potential is low (0V), it should output 9.95V, assuming Rds(off) =

I had assumed that this was the same problem as I was seeing in the signal switching part of the circuit -- the drain-source resistance being far too high when the mosfet is on; if I take Rds(on) = 165k (from earlier), the output with a 4k7 pullup and a 5V gate potential would be 9.72V to 9.95V, much closer to what I'm seeing in the simulation.

Increasing the pullup to 550k should set the output range to 1mV (5V gate-source) to 6.5V (0V gate-source), and although I don't see this from sims, I see something a lot better from the perspective of getting a good 0-10V swing at the output; 0.9V -> 9.9V.

This is all part of the stuff I don't understand: the simulations don't match my understanding; one of them must be wrong.

Would seem there may be some oddity with your sim program or fet model. Another sim shows the summing junction switches fast even using hulking great power fets or large capacitive loads etc. (perfectly balanced spice type fets) An interesting oddity remains though, in that the chopped sine wave is attenuated to about 2Vpp. Seems there is a very complicated charge transfer balancing act taking place during the sweep through the active regions of the fets handover, (time insensitive). Sort of like ... sine attenuation= fet Ron curve/fet Roff curve. regards john

It would probably be better to attach the substrate to a "large" negative potential. Note that (at least some of) the relevant low capacitances are measured with large negative substrate voltages. This may not fix all your problems, as I'm sure you realize by now, but it's a good start...

-frank

Hello Steve,

That 10M load resistor need to be many orders of magnitude lower. The gate charge needs some place to go and a 10M is like a brick wall.

Regards, Joerg

SD5401cy MOSFETs to make a fast

problems with the speed of my

understanding of things are

I've gone wrong

I tried

too

guys at linearsystems. They said that there is something

substrate connection (but didn't get back to me with

substrate should be grounded? There's only one

array.

It would probably be better to attach the substrate to a "large" negative potential. Note that (at least some of) the relevant low capacitances are measured with large negative substrate voltages. This may not fix all your problems, as I'm sure you realize by now, but it's a good start...

-frank

Hi Joerg,

I was hoping to keep a large load resistor, as I'm aiming for less than

I tried decreasing the load resistance to 20k and the edges did get a lot faster; about 170ns:

That's still not a fast as I was hoping though, and as can be seen from the first plot, I'm now dropping half the input signal voltage across the mosfets.

Won't the gate charge be able to go to ground via the other mosfet, which should be rapidly becoming 50 ohm?

Cheers,

Steve

By the way, looking at that graph, I don't see 330ns edges, they look more like about 100ns: rise times are usually measured from 10% to 90%, not from

In your diagram, the 69% point looks to take about 80ns. So if the capacitance you're charging is on the order of 10pF (from all the other capacitances people have mentioned, like Cgs and the capacitance across the resistor and so forth), you should be looking for a resistance around 8k.

Oh, and regarding the substrate, you probably want that to be at least as negative as the most negative circuit node: in this case, your 2Vpp sinewave means one of the MOSFETs is seeing -1V, at times.

Hello Steve,

With all the charge injection going on I don't think this will be easy. In those situations I usually create quad diode switches driven via a toroid. If it's all nice and symmetrical there is no charge injection. It used to be more expensive to do that but since the price for the SD5400 has gone up so much that is different now.

I thought they are 180 degrees out of phase.

Regards, Joerg

Yes, you are right, my mistake.

You mentioned that the gate charge needs somewhere to go. I've been thinking about it and I think you mean the charge on the gate-drain parasitic capacitance:

Initially, the "on" mosfet has a charge on the driver side of its Cgs and Cgd, and the "off" mosfet has a charge on the signal path side of its Cgs and Cgd. Then when the control signals switch, the previously on mosfet can discharge its capacitances via the (low) gate driver source resistance, and the Cgs of the previously off mosfet can discharge via the signal drivers low impedance. But the Cgd of the previousl off mosfet (and Cload) must discharge via the 10M load in parallel with the Rds of the other mosfet.

Is my understanding correct? If so, and assuming Cload ~ Cgd, and assuming this discharging of Cgd+Cload is the dominant cause of my slow edges, then if I remove Cload then the edge speed should approximately double. I tried this in a sim, but the results shows significantly faster edges - quite a bit more than doubling, which would suggest the charging of Cload through the mosfet is a lot slower than it should be (in addition to the number of other problems i appear to be having):

Thanks to everyone for their replys, they've been really helpful,

Steve

Hello Steve,

Think of it this way: There is a capacitance between the isolated gate and the 'path'. This means that there will be a Cgs and a Cgd. Injection happens when there is a change in gate voltage, positive or negative. When the FET is being turned on this will cause a charge injection on either side until the FET reaches a resonably low resistance. Then the charge has a chance to bleed off to wherever there is a low impedance node. But charge injection will already have happened on the node that wasn't connected to a low impedance while the FET hadn't yet reached its low RDSon.

When it is turned off the opposite happens. At first the charge injection won't be very noticable, provided there is a low impedance path on at least one side. When the FET transits into a higher impedance region there will be a charge effect on whichever terminal is not connected to a low impedance load.

Regards, Joerg