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Very basic clock questions.

Hi,

I'm making my way through the Virtex 4 user guide trying to get to grips with FPGAs, although I'm only a few pages in and already have a few questions:

- Why are there 32 global clock lines for a chip? It seems quite a lot...

- It states 8 global clock lines can be used in a single region, although why would you want 8 lines going into a single region? How does the region then know which clock signal to use?

- If each region is running at a different clock speed, how is communication between regions (and so different clock speeds) handled?

My apologies, I think that I'm asking questions which I should already know the answers to before I venture into the FPGA world. Looking at the previous questions in this newsgroup, these questions seem out of place; perhaps somebody could suggest some resources (books. etc...) to answer what appear to be basic questions that I have.

Thanks for your time, Nick.

Reply to
NickNitro
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Because it looks better than the 16 or 24 that the opposition offer! Realistically, a design is unlikley to use anywhere near 32 clocks, though the global clock lines can also be used for other global signals if you so wish. I guess one case where lots of clocks would be needed is if you have a number of indepdendent serial channels, each with a recovered clock.

Which clock is used is determined entirely by your design. All this feature does is ensure that in any region (quadrant?) of the chip one can mix logic using up to eight different clocks. The place and route tools typically handle the distribution of logic around the chip for you.

Carefully ;-) If you Google something like "multiple clock domains", or "crossing clock domains" then you should find a whole wealth of information on the subject. Typically you will need FIFOs or dual port RAM for data paths and synchronizing flip-flops for control paths.

Reply to
David Spencer

Thank you very much for the quick reply. :)

Reply to
NickNitro

Hi,

Yes, this may seem high at first. And it's indeed unlikely a design will use all of them. But that's on purpose, so that it doesn't become a limitation.

In a real life design, the number of BUFG tends to grow quickly.

Let's take a "simple" design where you receive a gigabit network flow, store it in DDR2, do some processing an display the result on a DVI screen :

- The gigabit ethernet is gonna take you 3 BUFG, one for the RX clock, one for the TX clock and one for your reference clock. - The DDR2 controller can take up to 5 BUFG (clock 125 MHz, clock 250 MHz, each one in phase 0 and in phase 90 + 1 BUFG for the IDELAY

200MHz clock) ... - The processing might be done at another higher frequency, so that's another BUFG - The DVI will also need it's BUFG.

So you see I'm already at 10 BUFG with a not so complex design ...

Each synchronous element in a region (FF, BRAM, ...) can choose independently what clock to use from those 8 lines.

You can cross clock inside region too ... and when you need to cross clock domain, you need to be careful. Depending on what must cross, the techniques vary ...

Sylvain

Reply to
Sylvain Munaut

Think of the resources published in the datasheet of an fpga as something that you have as your tools to achieve the design goals. So you may or may not use it. At times you may find that replicating the clocks can help the operating frequency by easing the loading on the clock tree and therefore you may be able to run the design faster.

-sanjay

Reply to
fpgabuilder

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