Hi,
I'm making my way through the Virtex 4 user guide trying to get to grips with FPGAs, although I'm only a few pages in and already have a few questions:
- Why are there 32 global clock lines for a chip? It seems quite a lot...
- It states 8 global clock lines can be used in a single region, although why would you want 8 lines going into a single region? How does the region then know which clock signal to use?
- If each region is running at a different clock speed, how is communication between regions (and so different clock speeds) handled?
My apologies, I think that I'm asking questions which I should already know the answers to before I venture into the FPGA world. Looking at the previous questions in this newsgroup, these questions seem out of place; perhaps somebody could suggest some resources (books. etc...) to answer what appear to be basic questions that I have.
Thanks for your time, Nick.