Using LUTs for array of coefficients

Sure- they could be conveniently stored in an SRL or RAM implementation of the LUT.

Most explicitly, you'll want to instantiate the RAMs or SRLs in VHDL. You can infer this sort of thing but I don't really see why you would. Simulation models can handle the simulation stuff and instantiation makes the synthesizers job all that much easier. It's generally easier to read the code, too.

Jake

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--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759

Hello Jake/Ray

I appreciate two esteemed people like yourselves offering me your advice.

I would rather infer than instantiate (if that doesn't sound too rude). The reason being that I have all the VHDL written and working in simulation and I don't have the time to redesign it. Right now I am hoping for quick fixes to cut down on flop utilization.

The following shows a few lines on my code....

subtype data_value is std_logic_vector(15 downto 0); type Array_A is array (0 to 15) of data_value; signal data_a: Array_A;

Are there any directives that I could enclose the signals data_a in to infer LUTs or SRLs instead of having to do instantiations..say for synplify ? I would really like to avoid instantiation if I can.

Thanks Bob

The best match in Stratix for these would be an M512 RAM (configured as 16 bits deep x 10 wide). One RAM will handle them all. Synthesis tools should automatically infer the RAM, and the Quartus fitter (place and route engine) will automatically decide that this best matches an M512 RAM and put it in one. So you shouldn't have to do anything too special.

You could also manually instantiate an altsyncram primitive in your HDL, but inferring really is more portable and intuitive.

Hope this helps.

Vaughn Altera

I suspect that inferring vendor-specific embedded primitives (like LUTs, RAM, etc) is one of the few situations where logic simulation is not reliable, as the implementation depends a lot on the translator. At least I had problems with xilinx BRAM that I could explain only in this way. Try at least one post-PAR simulation to see if the LUT behaves as you expect in all operating modes.

Tullio Univ. of Maryland

--

--Ray Andraka, P.E. President, the Andraka Consulting Group, Inc.

"They that give up essential liberty to obtain a little temporary safety deserve neither liberty nor safety." -Benjamin Franklin, 1759