How To: 3-input NAND gate using ACTEL ACT 1 logic module

Hello members...i need urgent help with a digital design problem

can some please help me expand the following function using shannon's expansion theorem

F = (A.B.C)' = C' + A'C + AB'C

I need to map this function to an Altera ACT 1 FPGA logic module with three 2:1 MUX's and one OR Gate.

any help would be greatly appreciated

thanks zaf

Reply to
zaf
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Don't remember "Shannon's expansion theorem". Can simplify using boolean algebra postulates.

C' + A'C + AB'C

= (C' + A')(C' + C) + AB'C = (C' + A') + AB'C =(C' + A') + CAB' =( (C' + A') + C)((C' + A') + AB') =(C' + C) + A')((C' + A') + AB') = (1 + A')((C' + A') + AB') = 1((C' + A') +AB') = ((C' + A') + A)((C' + A') + B') = ((C' + 1))((C' + A') + B') = (C' + A' + B')

or, using De'Morgan's theorem (A.B.C)' = A'+B'+C', you could've reached the above result instantly!

-- sincerely,

Russell Powell

Artisan Components SR. FAE - U.S. Central snipped-for-privacy@artisan.com

469-438-6589

Reply to
Russell Powell

It amuses me that student problems are invariably "urgent". By contrast, we who work in the commercial world of course have infinitely long timescales for our projects :-)

Not being an academic I have never heard of Shannon's expansion theorem, but Shannon was a pretty bright guy and I have no reason to doubt that he invented such a thing.

It's useful to remember that you can write a multiplexer as a Boolean expression:

Mux = in0.Sel' + in1.Sel

represents a 2:1 mux selected by Sel, with inputs in0 and in1. To help with this Mux description, let's define that as a function M(in0,in1,Sel).

So we can re-think your expression as multiplexers...

F = C' + (A' + A.B').C = C' + C.M(1, B', A) = M(1, M(1, B', A), C)

One more little observation: B' = 1.B' + 0.B = M(1, 0, B)

Hey, I got one over on your prof! I don't need that OR gate at all!

F = M(1, M(1, B', A), C) = M(1, M(1, M(1, 0, B), A), C)

|\ |\ 1-| | |\ 1-| | | |----F 1-| | | |------| | | |------| | |/ 0-| | |/ | |/ | C | A B

ASCII-schematic with thanks, as usual, to Andy Weber's wonderful AACircuit program

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-- Jonathan Bromley, Consultant

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Reply to
Jonathan Bromley

The OP is referring to ACTEL's legacy ACT 1 FPGA family, their very first but still supported. The basic Logic Module (LM) looks like so:

Please view in a fixed-width font such as Courier.

-- | \ A1 ---|1 \ | | | |------+ | | | A0 ---|0 / | -- | / | | \ -- | +--|1 \ | | | SA --------+ | |-> F | | +--|0 / -- | | / | \ | -- | B1 ---|1 \ | | | | | | | |------+ | | | | B0 ---|0 / | | / | -- | | | | SB --------+ | | | __ | S0 ---\ \ | | >----------------+ S1 ---/__/

Shannon's theorem refers to the MUX expansion as you already explained, but goes deeper into unique minterm expansion claims. Now try it- but wait a week so the OP cannot claim extra credit on his assignment.:-)

Reply to
Fred Bloggs

You have by DeMorgan's Theorem that (A.B.C)'=A'+B'+C' so the cofactor wrt C is A'+ B', and the cofactor wrt A of A'+ B' is B'- so the Shannon expansion is C'."1" + C.( A'."1"+ A.B'), and this agrees with your expression. Now use Actel's "logic WHEEL" function to map it-) and you are 10% of the way there-)

Reply to
Fred Bloggs

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