C-based FPGA programming/mixed languages

C is fine for programs that run on the processor core, if that is working. For hardware changes, your best bet is to modify and simulate the VHDL code you already have, or find someone who can.

I would hesitate to rewrite a working processor core in any case. Changing to a fledgling description language would further reduce your odds of success.

Anything is possible, but I would either stick with VHDL or start over. You will almost certainly be making interacting changes in both the new and old hardware descriptions -- and you will have to run simulations on the whole thing.

-- Mike Treseler

If it's a paying project, or a school project, consider using handel-C in the Celoxica product, or their newer System C offerings, for a mature production compiler. Mixed C and VHDL should be a minor problem with some planning.

Hello, I'm not sure synthesis tools exist for SpecC, since it was originaly dedicated to system specification. SystemC can be a good choice if you intend to write new modules. It is an IEEE standard and is widely supported in HW simulation tools and progressively by some HW synthesis tools too. Actually, the "synthesis" tools I've tested so far (Synopsys

-discontinued- and Prosilog compiler) translate SystemC to synthesisable VHDL or Verilog. Celoxica also support it but I've not tested their compiler yet. Generaly, the results are very good if your SystemC code is written in an "hardware-oriented" style. Concerning simulation, common commercial products (Modelsim, NC-Sim and probably VCS-MX too) support designs with modules written in the 3 langages mixed toguether thanks to component wrappers. Well, it's true that SystemC is easier to use from the syntax point of view when you're used to C++ langage. But you have to keep in mind that if you code your modules in a software-like style, you take the risk of obtaining inefficient and buggy hardware. Knowledge of hardware-oriented coding style is still required to obtain good results. In particular, some basic concepts must be mastered like the difference between signals and variables, usage of for loops, etc.. Last bu not least, you'll probably have to debug the VHDL code anyway, so it should be usefull to have some langage knowledge.

Best regards

Manu

The Other Guy a écrit :

Hi,

Thanks for your response. It certainly explains why I can't see any documentation on SpecC and synthesis.

I will investigate SystemC some more, although as it is based on C++ classes, it was a route I was hoping to avoid (I prefer C). FpgaC appears to be able to output VHDL as well, but I have been unable to get any output from it that looks like it does anything other than initialize values to 0.

C -> VHDL is probably the best option, it will help me learn VHDL as I go.

The Other Guy

Usually the language VHDL itself is not the problem ... You will have to learn a new syntax and if you start with a small example with a clocked process you should be able to successfully modify that within a few days ...

another problem is the tool-chain ... you just don't click make and everything is fine - the workflow is different, there are timing constraints to take care of and lots of warnings (and only few of them are relevant ;-)

The biggest problem comes with "thinking in hardware" which turnes out to be quite a problem for C-people ... the sequential way of planing your programm usually does not fit very well and will waste a lot of ressources ... To get a deep understanding about whats really happening inside and why some description is not very clever will take you well above .5 years

I've never tried any of those high-level languages but I doubt they will solve the 2nd and 3rd problem ... they may hide it though ;-)

bye, Michael

Yeah, that has been a pain for me too. Variable initialization is very high on the features development list for FpgaC as the cost to create a mux and assign values is much higher than "free' as initialization would offer. I'm not sure yet if it will be included in Beta-3 during April, or Beta-4 during June, but it will be part of one of the next two beta's.

The right vhdl template and design rules can cover most of the "thinking in hardware" bit and still allow a single threaded hardware description using variables, functions and procedures.

See this discussion:

-- Mike Treseler

C-people are hardly all the same cookie cutter experience levels, any more than hardware engineers are. Many have both the experience and skill levels to do C based hardware design with modest training on the tools. There are embedded, device driver, and parallel programming C-people that are very used to concurrency in their programming styles.

Again, when you say "you", it's probably an unfounded generalization without any understanding of the OP's training, experience, or skills. Such blind generalizations are ....

no offense intended - I don't know the OP and his skills

It is my personal experience with "software" colleagues and students trying to start with FPGA projects ...

It just takes some time to get familiar with those concepts and workflows ... if you know how to think in hardware, then VHDL should not be the big problem.

bye, Michael