Hi all,
I am targeting my design to XCS200 -5 fg256(SPARTAN device) . My OFFSET OUT timing constraints are very tight.So inorder to decrease the PAD delay i am forced to set the drive strength to 24 and SLEW=FAST. only 2 pins of the 137 I/O's which i am using have a drive strength of 24 rest of them have a DRIVE=12.
Can anyone tell me what is the significance of this DRIVE strength in REAL time.Will it create any problems having a DRIVE=24 in real time??.
Thanks n rgds, prav
If you aren't already using a DLL, you might consider it. It can remove several nanoseconds of clock-to-output delay. These are available in the device you're using.
Increasing drive strength can cause problems with simultaneous switching such as ground bounce. Xilinx's documentation should have guidelines telling you how many drivers of each strength you can use within a bank before having problems, but these are only guidelines.
Hi jamie,
I am already using the DPLL, but by using the DPll how will it reduce the PAD delay.I want the PAD delays to be less.
rgds, prav
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