two I/O markers on the same wire

I use xilinx shematic editor. On a wire i trying to place two I/O markers (same name ?), but the editor say : "Error : net 'xxx' is already a port with a polarity value 'output' "

I want do this for wiring facility on the uper level schema.

Any solution ?

Thanks

Usmgn

Reply to
usmgn
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"

think! (sometimes helps)

add a dummy buffer to split the wire before connecting to iopad/marker

antti

Reply to
Antti Lukats

I had thought of that but i was not on that would not have perverse effects (i debute with FPGA).

Thanks for your help.

usmgn

Reply to
usmgn

It will have no effect. The synthesis just gets rid of anything that doesn't affect the final outputs of the logic.

Jon

Reply to
Jon Elson

(someone wrote)

Quartus has a logic device that looks like a buffer, but is called a wire. It separtes markers so one can connect wires with different names.

But yes, for FPGA synthesis you will find that even inverters disappear into the input of the next CLB, or the output of the previous one. A chain of inverters cannot be used for delay without special indication for the software not to optimize them away.

-- glen

Reply to
glen herrmannsfeldt

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