Hello all, I am trying to implement a DSP algorithm on a FPGA(SpartanIIE). I was wondering if somebody could comment on whats the best way to truncate the multiplier outputs to the 8bit inputs I have. If I have 8bits inputs to the multiplier I want the output to be 8bits too instead of
Thanks, Sourabh
I plan to have it "unsigned".
downto 0),
a '1'.
Truncation simply adds a DC offset to the signal which is not a problem if you're bandpass or highpass filtering just downstream. Although rounding gets rid of the DC offset it will add an additional adder operator with associated carry-chain resulting in increased propagation delay and LE resource utilization in your datapath. This may have an impact if your design is tight on resources or high speed.
-Paul
...although often you can implement the additional adder by using the 'carry in' of a downstream adder. Cheers, Syms.
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