Algorithm to Hardware ?

Hi, I'm trying to implement a sinusoid extraction algorithm (see code below) on a SpartanIIE FPGA. I would appreciate if somebody could help me on starting to write the VHDL code from the matlab algorithm I have. I need a direction to start from, I dont have experience with DSP on FPGA before.

f=30;T=1/f; fs=11025;Ts=1/fs; n=10;z=pi/4; u1=50; u2=500; t=0:Ts:n*T; x=length(t); u=sin(2*pi*f*t+z); A(1)=0; Phi(1)=0; for k=1:x y(k)=A(k)*sin(Phi(k)); e(k)=u(k)-y(k); A(k+1)=A(k)+2*u1*e(k)*sin(Phi(k))*Ts; Phi(k+1)=Phi(k)+(2*u2*e(k)*A(k)*cos(Phi(k))+2*pi*f)*Ts; end figure(1), subplot(211), plot(t*1000,u),subplot(212), plot(t*1000,y)

I would need lookup tables for sine and cos implementation. Can I use the look uptable IP core available from Xilinx?? if yes is it free? I am using the ISE webpack which is available for free download. I would need a headstart how to start converting my algorithm to VHDL. Please advise.

Thanks, SD

To start, consider how it would be implemented in TTL chips, gates, flip-flops, counters, RAMs, etc.

Very convenient to divide in matlab, but it takes a lot of logic to do it in an FPGA. Much better to use T and Ts as constants. Most likely they should be scaled fixed point (the binary point not directly to the right of the LSB). How many bits do they need?

Xilinx provides for RAM and ROM (initialized RAM). You need to supply the data. There is no charge for initializing RAM, you supply the bits. This should be relatively easy if you generate one k value, one A and one Phi, per clock cycle. If you want more, it gets complicated fast.

If you are doing it in floating point in matlab, I would try converting to fixed point in matlab before trying to convert to VHDL.

-- glen