Six months after I said "it's nearly done", I've now finished an alpha-test version of the synthesisable VHDL fixed-point package I promised. Doesn't time fly when you're enjoying yourself? :-)
I've published it on our corporate website but, as yet, there are no links to it from elsewhere on the site. So you need to go straight to it using this link:
At present, all you get is a VHDL package and package body, and a PDF doc describing it.
Any feedback is welcome. Please note that it is very much in an experimental state at present. It is in desperate need of example designs and a validation test suite; contributions towards either will be gratefully received, and acknowledged in future releases.
I would be especially grateful for any indication of whether it's aiming in the right direction, and how it could be enhanced or made more useful.
My employers are not responsible for any part of the package. Any comments on it should come directly to me at the address given below.
-- Jonathan Bromley, Consultant
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