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vhdl construct problem

Hi, In my vhdl code, on construct is as follows case to_integer(addr) is when to_integer(fifo1_base + fifo_status )=> Where addr is signal of type unsigned(11 downto 0) and fifo1_base and fifo_status is constant of type unsigned(11 downto 0) I tried to compile my code in Cadence tool(ncvhdl) and modelsim. In both the cases it said for "when" statement expecting a locally static statement. But surprisingly the code got compiled successfully in quartus. Where is the problem while trying to compile with cadence and modelsim? I am using vhdl 93 flag.

Reply to
sudip saha
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Quartus is bending the rules here.

Create another constant:

and use that in your case statement.

(By the way, this is purely a VHDL question and would be better directed to comp.lang.vhdl)

-- Jonathan Bromley, Consultant

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Reply to
Jonathan Bromley

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