Hi,
I am new to electronics and VHDL etc.
I am trying to understand the first 2 bit counter example. In this PDF:
I think the clock signal goes as follows: high, low, high, low, high, low.
So that's just the same as:
101010101010101010101The clock signal is connected to a T_flipflop and goes out port Q0 (and also ff0 I dont understand what that is... just some internal state thing ? but ok)
So after the clock signal passess through the T_flipflop the new signal will look like: old clock signal:
1010101010101010101010( t_flipflop is explained at
new Q0 signal:
1100110011001100110011Now the new Q0 signal also goes to another invertor...
So after the invertor the interver signal will look like:
( I think an invertor just inverts it right ? ;) )
Q0 inverter signal:
0011001100110011001100Now the Q0 inverter signal enters another t_flipflop and it's output is Q1. (also ff1)
Q1 signal:
001000100010001000100So now we have three signals:
The original clock signal:
101010101010101010101010The Q0 flipflop signal:
110011001100110011001100The Q1 flipflop signal:
001000100010001000100010Ok I find this a little bit weird.
For a counter I would expect the output to be the following: Q0 Q1:
00 01 10 11 00 01 10 11However the output seems to be:
10 10 01 00 10 10 01 00 10 10 01 00 10 10 01 00 10 10 01 00 10 10 01 00This is totally different than how I would expect it too work...
Have I made a mistake in my reasoning somewhere ?
Is there a part I dont understand ? maybe the invertor works differently ?
Or is the PDF/manual a weird/bogus/wrong example of a 2 bit counter ???
Bye, Skybuck.