Using low-core-voltage devices in industrial applications

A linear regulator should keep the core as clean as is needed for the devices to operate reliably. I/O voltage(s) remain the same.

Remember that most modern devices are not able to deal with much more than 3.5V I/O... so if some of the industrial things you are interfacing to are still in the 5V world, you'll have to get inventive (opto's maybe? relays?)

Have fun,

Marc

...and a switching supply will work fine too. In fact, I'd bet that a switcher solution is smaller, because you don't need so much heatsinking, and more reliable as your circuit will be operating at a lower temperature. Remember, you're throwing away all that energy in the linear regulator. Design of a switcher is pretty easy too; can you copy a demo board layout? Cheers, Syms.

To achieve high reliability on low voltage cores, keep in mind to be careful to follow the power on ramp rate requirement of each voltage. For example, the Xilinx Virtex 2 Pro series can have 4 power voltages:

3.3V I/O power, 1.5V FPGA core power, 1.8V PROM core power, and 2.5V auxillary power. The core power for the FPGA and the PROM have a minimum and maximum ramp rate. I had to add large capacitors to the LDO regulator outputs in order to meet the minimum ramp rates.

Also, be careful to look for any voltage sequencing requirements the FPGA may have. Sometimes the order the various voltages come up does not matter, but sometimes it does.

John

Hmm, nasty. Next time you may want to consider using a simple RC network in the feedback path to limit the ramp rate. Cheaper, smaller and without enormous amounts of current being dumped from the supply into your monster output capacitors. Most modern switching circuits (I use the easy to use LTC3414) have 'soft start' modes which limit turn on current. Cheers, Syms.

Hi Marc Randolph,

Altera's Cyclone devices will go to about 4.1V before cracking up. Don't know how hardy the Cyclone II devices will be though.

As an aside: I did find a neat trick regarding ESD stuff about Cyclones: the built-in PLLs are a wonderful way of filtering high-frequency noise from your board clock. Just put one of the PLL's outputs in 1:1 mode. Any external noise inserted on the clock trace will of course influence the VCO in some way, but in the output of the PLL this will be visible as some amount of clock jitter, not as a whole clock spike. Of course the 4.1V constraint is in effect here too.

Ben

eliben,

I was waiting for all responses to trickle in before wading in.

Why would any technology be less reliable?

Are you concerned about the robustness of the technology to overvoltages?

If this is the case, this is beyond the issue of reliability, it is an issue of not liking the absolute maximum ratings, which have gotten lower as the technolgy shrinks.

Again, this has nothing to do with reliability.

If you apply 1000V to a 110V light bulb, it will blow out. Is it less reliable? No, it is not.

If you can not prevent voltage surges inside your environment, then you should be using 4000 series 15V CMOS (or better yet, tubes).

If you can prevent voltage surges, then you are free to use any technology you choose to.

90 nm Spartan 3 and Virtex 4 have the same predicted operating life as 220 nm Virtex or Spartan 2.

How is this possible? Well, it is easy: we design to meet a desired life, and we do not do anything that would cause the device to have a shorter lifetime. Foundry rules.

As for comments on ramp on power supply rates, etc. these all have nothing to do with your basic question, and also have nothing to do with reliability.

As for power supply design, consult National, TI, Bellnix, Linear Tech, Intersil:

Take your choice, and all of these suplliers have pre-engineered solutions for you that Xilinx has already validated.

One more comment, new (since Virtex II) FPGAs (from Xilinx) have no power on SURGE behavior on the core supplies.

Older Xilinx products had small surge levels (~ a few amperes worst case in the 4K and early Virtex and Virtex E days).

Some 130 and 90 nm FPGAs (from other vendors) have LARGE SURGES and also LARGE LEAKAGE currents which necessitates careful power supply design (and lots of power).

And it isn't just the core supply either. Note the start up power on the other supplies as well (might need to consult the vendor's spreadsheet tools on their websites).

See page 3: "Stratix II FPGA Power Requirements1 VCCINT (core voltage) 1.15 V min, 1.2 V typ, 1.25 V max ICCINT (core current) EP2S15: 4 A max Inrush to start-up included EP2S30: 6 A max EP2S60: 7 A max EP2S90: 9 A max EP2S130: 12 A max EP2S180: 16 A max"

Please read my old (now) tech note on the subject:

Austin

I use a Cyclone on a gate drive for a high power IGBT - a VERY noisy environment. The precautions I took were :

- Convert I/O to/from 5v directly adjacent to the device. The higher voltage signals then proceed around the PCB

- Around the FPGA itself, create multiple ground/power planes - including one on an external layer to serve as a shield

- Make provision for additional shielding (i.e. copper planes mounted above the FPGA sub-system) - didn't use this in the end.

- Use an accurate linear reg. and set the internal voltage at the upper end of the tolerance

I don't know which of these were important, but the device has performed like a champ

I do have a concern concerning longevity (often much more important in industrial stuff than commercial). This is to do with the stability of the sub-micron geometries used in devices such as this. To alleviate these concerns, I make sure it runs really cool. I don't know if anyone else can comment on this concern.

Gary

In my experience, questions like this refer to operational reliability, not device MTBF.

So to answer the question in this context : Yes, a lower voltage device has lower voltage margin, so it is less tolerant of the same ground noise. Even worse, from an industrial context, 90nm devices are faster, so they can 'see' a spike older devices simply miss.

Some semiconductor vendors graph pulse width / pulse amplitude for disturbance limits, but I have not seen this for FPGA.

Thus an industrial user is right to be cautious, and should include field tests in the design.

Arcing contacts : Relays, Motor brushes, contactors etc can easily generate sub-ns wavefronts at hundreds of volts.

You can run a spice simulation, to see how much coupling C is needed, to generate (say) a 1V bounce in 10nH of trace inductance. A good practical noise generator is a relay that self-commutates, and switches mains. Or Piezo gas lighters...

-jg

Gary,

As I said in my post, if one follows the foundry rules, there is no reason why 90nm should not last at least as long as any earlier technology.

Heat is the enemy for all silicon devices, so keeping power dissipation down is always a good thing.

That is why we are quite happy with the advantages we gained from the triple oxide technology in V4: half to 1/3 the leakage of other large

90nm FPGAs, 40% the dynamic power of the 130 nm Xilinx V2 Pro (fabric), and no start up surges.

Aust> I use a Cyclone on a gate drive for a high power IGBT - a VERY noisy

I always wondered about the volatile configuration memory getting corrupted. Any comments on that issue?

David,

This issue is at least as old as the static configuration latches that are used to hold the configuration:

what will cause config bits to change?

In order to make FPGAs work (at all), one has to start with a very robust memory cell design. NOT SRAM!

We use specially engineered (for the myriad of requirements we have) cross coupled CMOS latches.

They can be slow.

They can be heavily loaded (the more loads the better).

They must run at the highest internal voltage we have to be used to control the pass gates (also good for stability).

They must be immune to read disturb (as we can readback while operating).

They must be easy to write.

They must be very low leakage.

They must meet our SEU (soft error upset) reliability criteria.

If the power supply itself glitches, the POR (power on reset) circuit uses dummy memory cells to detect if they can be upset (selected sizes of loads to mimic the most sensitive memory cell). So, if there is enough of a power supply glitch to flip a memory cell used for configuration, the POR will trip, and the device will reconfigure (as it lost it memory from the glitch).

How else can you flip those bits?

1) Place in nuclear reactor 2) Inject massive amounts of current into the substrate by excessive undershoot (as in many many amperes from a bunch of IOs switching at once -- exceeds the Latch up spec, but no latch up will occur, just de-programming) 3) exceeding the absolute maximum specifications in other ways we haven't dreamed of (yet)

Austin

There have been other threads on that. The config RAM is slower, and more immune to radiation upset, than the smaller/nimble logic. But it can still happen, so the mission critical systems usually have the ability to re-config.

-jg

The "other large 90mm FPGAs" being Spartan 3?

I thought Spartan 3 already had that? If so, how is it a feature of "triple oxide technology"?

Thanks for the info. Now I fell better. We are using Spartan II, IIe and IIIs in out brusless motor drives. Which have large voltage and current swings up to 340 volts and 18 amps, and only inches away form the FPGA!

Dave Colson

(snip)

Consider timers like:

Well, likely not FPGAs but I believe they are digital electronic devices with memory.

Most of these not only have to switch loads like 120V and 4A, incandescent or some fluorescent, they are powered by such current. (One can switch 15A 277VAC, though it has help from a battery.)

At least one, and I believe all, are series connected with the load being controlled. When the switch is off, the have 120V AC power. When on, less than 1V at 300mA or more. Some have a battery for backup, but not all do.

-- glen

Eric,

"Large" is not in S3 vocabulary. They (Spartan) have no "large" devices.....by definition. If it is "large" then it belongs to the Virtex family.....also by definition.

That said, the 3S5000 is a pretty "large" part, but still a lot smaller than the XCV4LX200 (largest V4 basic logic device).

S3 also has no start up surge. Yes.

Triple oxide is not required in order to control the surge, but it doesn't hurt (offers even more options to the designers). V2, V2Pro, and S3 are all dual oxide, and they all have no surge.

Aust> Aust>

David,

You must still beware of induced magnetic fields (which can not be enitrely shielded by any means).

A 1 turn transformer from your motor to the wiring of the pcb may be an issue.

Be sure to have someone look at how much induced voltage there is in the loops present in your PCB from the motor fields.

If the magnetic field can be held at 90 degrees to the PCB loops, then it will not be an issue (no transfomer effect).

Aust> Aust>

That seems fishy. Won't that also screw up the transient response when you are running normally?

Cheaper, smaller and without

Soft start is good. They aren't common on the low cost switching chips I've been looking at recently.

LTC3414 looks good. (But that's only from a quick glance at the data sheet.)

--
The suespammers.org mail server is located in California.  So are all my
other mailboxes.  Please do not send unsolicited bulk e-mail or unsolicited
commercial e-mail to my suespammers.org address or any of my other addresses.
These are my opinions, not necessarily my employer's.  I hate spam.

The ICC values listed for Stratix II in the TI reference guide above are out-of-date. Altera has requested that TI update this document.

EP2S180 users can expect from 1.8A to 5.3A of ICCint current during FPGA power-up, depending on the temperature and the silicon characteristics (typical vs. the process corner that leads to maximum power). Given the high-density and high-performance of the 2S180, these values are below the operating current for the vast majority of customers.

While other FPGA vendors only specify values for typical silicon at 25C, Altera provides start-up currents and operating power values at various temperatures and for both typical and worst-case power process corners.

For a power estimate specific to your design, use the PowerPlay Early Power Estimator, available at

mator.html. If you have a completed design, you can use the Power Analyzer built into Quartus for even more accurate answers. See for details.

Vaughn Altera v b e t z (at) altera.com [Remove spaces and insert proper @ to reach me]