NIOS: Run program from SDRAM

Apr 17, 2004 5 Replies
M

Hi, I have the NIOS developer board with APEX FPGA.It has a SODIMM socket for SDRAM module. I use a Micron MT8LSDT864HG-10ECS. I make a Quartus project based on verilog/standard_32. I use nios_32 CPU. I create a new memory configuration based on Micron datasheet and I put it into class.ptf from altera_avalon_new_sdram_controller. I write a simple program that can read and write memory maped in sdram. This configuration has Location Vector, Program and Data memory set to ext_ram which is SRAM. But next I change Progam and Data memory to sdram. Program is compiled correctly and srecord looks ok. I load it to board using nios-run. When program starts it prints only "Return address is 0x00000000" and returns to GERMS. The same situation is which all demo programs from cpu_sdk and my own programs. I will be very thankful for any help. Best regards, Maciej Witaszek


Maciej Witaszek nospam_mwitaszek@elka.pw.edu.pl remove "nospam_" from my address
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P

Hi Maciej,

Have you tried SignalTapping it? I've had similar problems, and found them pretty quickly by SignalTapping the Nios instruction and data pointer (IIRC, ic_address and dc_address) along with the Avalon signals going to/from external RAM. I think some of my problems ended up being stack corruption, I/O drive strength, and corruption with simultaneous multi-mastering.

-- Pete

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J

On Sat, 17 Apr 2004 21:58:26 +0200, Maciej Witaszek napisal:

I got SODIMM from laptop and compiled some simple design (only with UART & lcd). Worked from the first time. Board was the one with Apex20KE,

Have you tried "minimal_sdram_32" from examples directory?

PS: To juz taki czas, ze rodacy szukaja pomocy za granica? :-)

Jerry
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M

Hi jerry1111, where did you find "minimal_sdram_32"? I coudn't find it in Quartus 3.0 and

4.0 both Web Edition and in NIOS dev kit. I'm working now on my own design so it's posibble that I mixed up a wiring. I simulated a cpu with Verilog model of SDRAM from Micron and cpu read instruction from SDRAM. It looked ok. I don't what I'm doing wrong :(

Best regards, Maciej

PS. Milo, ze w Polsce tez sie ktos tym zajmuje :)

Maciej Witaszek nospam_mwitaszek@elka.pw.edu.pl remove "nospam_" from my address
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K

and

Maciej,

This may not pertain to the Apex board sample designs, but the Cyclone samples had a few ns delay on the SDRAM clock. My custom design with the same exact SDRAM chip had to have this delay removed. I was of course happy with this as I now have an unused pll available.

Ken

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J

Strange, but it disappeared in Nios 3.10 I can send it from older versions, but you must contact me on priv (watch out for anti-spam mail). That design was working, because I was in need of having huge data buffer.

A milo sie dowiedziec, bo myslalem ze nikt tego u nas nie uzywa...

Jerry
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