Spartan3 LVCMOS33 Slew rate

From fpga open driver to 150 ohm pull-up and then to 100 Ohm series termination close to the receiver. I used open drain is because I needed to generate 1.8V output.

Can you please also respond my question about Peter's suggestion of using the top transitior until it reaches high threshold of 1.5V? My concern here is that the fpga fabric will have fair amount of prop delay before it turns off the top fpga transistor.

close to the receiver. I used open drain is because I needed to generate 1.8V output.

top transitior until it reaches high threshold of 1.5V? My concern here is that the fpga fabric will have fair amount of prop delay before it turns off the top fpga transistor.

It is NOT necessary to use an open drain. It's not even a good idea. So Peter's trick is not needed.

John

termination close to the receiver. I used open drain is because I needed to generate 1.8V output.

top transitior until it reaches high threshold of 1.5V? My concern here is that the fpga fabric will have fair amount of prop delay before it turns off the top fpga transistor.

Test01, If the VRP and VRN pins for the bank in question are unused, you might consider adding a couple of resistors to them, changing the buffer to LVDCI_33. Maybe you need a couple in parallel, and changing the "series" 100 ohm resistor located at the receiver to 60 ohms parallel and getting rid of the pull-up. Just a thought in trying to avoid splicing a series source resistor at the FPGA. I think this may be another way of doing what John suggested.

-Newman

termination close to the receiver. I used open drain is because I needed to generate 1.8V output.

the top transitior until it reaches high threshold of 1.5V? My concern here is that the fpga fabric will have fair amount of prop delay before it turns off the top fpga transistor.

Test01,

Well, maybe not because I did not consider what the transition from 1 to 0 would look like at the receiver with the parallel termination.

-Newman

John,

I am all for driving 3.3V pushpull instead of open drain from Spartan3 FPGA but ultimately yhr receiver needs to see 1.8V signal without adding any blue wires to the board. From the FPGA driver I have 150 ohm pull-up to 1.8V and then I have 100 Ohm serial resistor to the receiver. The receiver internally has resistor that varies from 400 Ohm to 700 Ohm. Keeping this termination sceheme in mind, I am trying to figure out how I can drive LVCMOSS33 Pushpull? Since this board is in production I can not add pulldown resistor and such.

Thanks for your feedback.

Newman,

Unfortunately, I do not have liberty to use the VRP and VRN pins. From the S3 FPGA output pin, I have 150 Ohm pull-up and then ohm series resistor close to the receiver. I can change the values of these resistors. I was thinking about driving the FPGA output pin 3.3V push-pull and then remove the 1.8V pull-up but increase the series terminatination value.

ultimately yhr receiver needs to see 1.8V signal without adding any blue wires to the board. From the FPGA driver I have 150 ohm pull-up to 1.8V and then I have 100 Ohm serial resistor to the receiver. The receiver internally has resistor that varies from 400 Ohm to 700 Ohm. Keeping this termination sceheme in mind, I am trying to figure out how I can drive LVCMOSS33 Pushpull? Since this board is in production I can not add pulldown resistor and such.

Is your circuit....

+3.3 | | 150r | | | 60r trace fpga----------+==============================================----100r----load

?

John

All,

I simulated a GTLP IO cell, with an external 50 ohm pullup to 1.8 volts driving a 60 ohm pcb trace. At the end, I have a split 100 ohm termination, to 1.8V and ground.

1.8 volts 1.8 volts | | 50 ohms 100 ohms IO pin | 60 ohms | GTLP----|-===============================----Load | 100 ohms | GND

VERY FAST rise and fall times (2 volts/ns). GTLP will be the fastest possible IO standard you could select for this. It is by the standard, open drain (uses the 50 ohm external R for pullup). No need to mess around with trying to control the tristate when pulling high (as GTLP can't pull high internally).

The above is the recommended (and simulated) solution. An alternative to the split 100 ohm termination is a single 50 ohms to a 100 pF capacitor to ground, or 50 ohms to 0.9 V termination supply.

Aust> >

but ultimately yhr receiver needs to see 1.8V signal without adding any blue wires to the board. From the FPGA driver I have 150 ohm pull-up to 1.8V and then I have 100 Ohm serial resistor to the receiver. The receiver internally has resistor that varies from 400 Ohm to 700 Ohm. Keeping this termination sceheme in mind, I am trying to figure out how I can drive LVCMOSS33 Pushpull? Since this board is in production I can not add pulldown resistor and such.

FPGA output pin, I have 150 Ohm pull-up and then ohm series resistor close to the receiver. I can change the values of these resistors. I was thinking about driving the FPGA output pin 3.3V push-pull and then remove the 1.8V pull-up but increase the series terminatination value.

Test01, I'm no expert, but series termination values are typically located close to the source and are used in point to point connections. End terminations are parallel and terminated to the characteristic impedance of the transmission line. The case under discussion now is one that I have never encountered. I saw the hyperlynx demo do an AC termination. That was cool. If the connection from the FPGA is a transmission line and it is not terminated properly, you can expect reflections that manifest themselves as more ringing. Do you see lots of ringing going from high to low? Some IC's have an input clamp diode to VCC IO that can clamp the voltage if the input current is limited by a series resistor to a safe value. That hyperlynx tool is cool. I wish I had it. Maybe you can talk your boss into getting it. Thanks Symon for the link. I am really out of my environment on this topic, so take my observations with a grain of salt. Sometimes it is best to change the design even if it is in production. Many boards have different rev levels. It's a tough call.

- Newman

Austin,

yes. from FPGA LVCMOSS33 Open drain output, I have 60 Ohm tranmission line and then to 150 Ohm pull-up to 1.8V and then from there to 100 Ohm series resistor to the load. By looking at the waveform, we are seeing some ledges (steps) on the rising edge.

My solution to acheive better slew rate will be to lower the pull-up resistor value down to 60 Ohms and lower the series termination down to 22 Ohms. 60 Ohm pull-up termination will be close to the tranmsmission line impedance of 60 Ohms. By looking at the V-I curve the bottom transistor voltage drop is about

200mV at 15.6 mA. This translates to only 12.8 Ohms of ON resistance. Thus I can afford to lower the pull-up resistor down to 60 Ohms. This will still give me 400mV low swing.

Is that correct?

Austin,

So those VREF pins can still be used as user I/O pins if I use GTL output? If so that will be great. I tried using one GTL output and the constraint editor assigned the output as GTLP and the I/O Pin corresponding to VREF was assigned as VREF PIN. This is why I am asking.

THanks.

Yes,

You may have to hand edit the ucf file, and check that the VHDL or verilog is not instantiating any input.

The Vref pin is only used if you have a standard that uses an input comparator in that bank.

Aust> Austin,

so that will be great. I tried using one GTL output and the constraint editor assigned the output as GTLP and the I/O Pin corresponding to VREF was assigned as VREF PIN. This is why I am asking.