Spartan 3E Sarter Kit Ethernet

Look at this site, there are some information:

Yes you can, but it would be easier with the Microblaze, or a sufficiently powerful soft processor.

I think AccelDSP works with Simulink (MATLAB), not with C code. System Generator should be a tool for developing DSP apps, probably it's best suited for your needs.

Andrew

You transmitt ethernet packets by waiting for the PHY transmitt clock to go low "always @(negedge E_TX_CLK)". Then set E_TX_EN=1 and E_TXD[3:0]=first nibble. Then for every event set next nibble. Once you have supplied all data. Set E_TX_EN=0 to complete packet. You have to wait 24 cycles at 100M before sending a new one. The nibbles shall be 555555555555555D - packet data - crc32. Crc32 is calculated from packet data only.

If it is acceptable to hardwire the IP and MAC addresses, then a fairly straightforward state machine, in combination with a prepared header can transmit UDP frames. This can be a reasonable solution for a quick hack on a lab.

For local networks it is also reasonably safe to omit the UDP checksum. This can be done by setting it to an all-zeroes value. By doing so, you can avoid making an extra pass over the data.

However, if you need things like ARP, DHCP or IP routing, using a Microblaze (or another core of your choice) would make more sense.

Actually, you can calculate the CRC on the fly because it is transmitted last.

The Ethernet layer CRC-32 is transmitted last, but the UDP checksum is in the header.

Beware that omitting the UDP checksum removes protection against data corruption inside the FPGA, e.g. a bug in the transmit path before the CRC-32 is applied.

You can do this a number of ways, but the easiest would be to use a processor based subsystem. Build a system using BSB with MicroBlaze + ethernet. Add lwIP for a TCP/UDP software stack.

The right solution would depend on your application ofcourse.