Spartan 2e implementation

jose wrote: : Hi,

: I m new in FPGA. : I m sure that someone has for me an answer to my issue. I work with : XC2S300 of the Spartan Familly. when I implement I get the following : warning message:

: Warning: NgdBuild: 477 - clock net 'clk_bufgp has non clock : connections. These : problematic connections include pin i1 on block u1_io with type LUT2 : ..

: I try to do gating clock.

First rule: Don't use gated clocks, use the CE input instead.

: What I can do?

Second it looks like you bring in a signal through a clock input, but don't use it as clock, e.g. you use the input clock as input to a logic gate and you feed the output of that gate to the clock network.

Bye

Hi,

I m new in FPGA. I m sure that someone has for me an answer to my issue. I work with XC2S300 of the Spartan Familly. when I implement I get the following warning message:

Warning: NgdBuild: 477 - clock net 'clk_bufgp has non clock connections. These problematic connections include pin i1 on block u1_io with type LUT2 ..

I try to do gating clock.

What I can do?

OK in general; Clock gating sucks, don't do it.

In specific; An asic I was involved with had a clock gating circuit (I call them precision kluges). To test the design in the fpga I just ran the gated clock out of the chip, then back on using a dedicated global clock buffer. This worked great, and the fitter didn't complain either.

je