Simultaneously Switching Outputs in Spartan-II

Oct 19, 2004 2 Replies
C

Hi all,



I am trying to figure out the pin allocation for a Xilinx Spartan-II device in the PQ208 package that is to implement a PCI agent (target and master). The initial approach was to connect all IOs from banks



6 and 7 and parts of bank 0 and 5 directly with the card edge traces in the order given by the card edge pin assignment. Banks 6 and 7 collectively provide 36 IOs whose supply is provided by 5 Vcco/GND pairs. Given an SSO recommendation of 4 IOs per Vcco/GND pair for PCI, the approach does not seem to be feasable with an example of a master driving a 0xffffffff (that's 32 switching IOs alone for the AD lines) on the bus. Since I believe that it's not the first time that a Spartan is used for PCI agents, how serious are the SSO guide lines to be taken ? Am I overestimating the effects of ground bounce in PCI designs ?


Thanks and regards, Christian Boehme



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H

There is an interesting discussion of this area for Spartan3 going on. Subject is "spartan 3 on 4 layers" (this newsgroup)

No simple answers though.

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C

Found it. And it's highly interesting (if not controversial).

Cheers, Chris

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