Hi folks,
In the context of a research project, we are currently working on a IDE Hard drive interface targetting the Spartan-II/Virtex architecture.
On our prototype we simply used PIO mode, but we would like to extend our controller so that it can handle UDMA.
The problem is that we just realized that this protocol is somewhat tricky, more specifically we are concerned on how to implement "source synchronous" aspects of the protocol expecially for read operation (see below).
_______________ ____________ __________________
\ / \ / Data ??? X Valid Data X ??????
_______________/ \____________/ \________________
5 ns
_________________ DMARdy / \ _______________________/ \________
DMARdy and DATA are both sourced by the hard drive side.
According to the IDE/ATA spec (or at least what I understood from it) the data should be sampled on a rising edge of DMA_Rdy.
To us, the most simple solution would be to use the DMARdy as a clock signal to sample the data in the IOB registers, then re-synchronize to the FPGA system clock with another register. However, we are not sure that this is a safe approach with respect to signal integrity.
Besides, we realized (too late, of course) that the DMARdy pin of the IDE drive is not connected to a GCK pin ...
Would anybody have somme idea on how to solve this issue ??
Thank you very much in advance.
Steven