IDE Ultra DMA on a SPARTAN II (corrected version)

Hi folks,

In the context of a research project, we are currently working on a IDE Hard drive interface targetting the Spartan-II/Virtex architecture. One important point is that the drive is not connected through a ribbon cable but rather directly to the Board through a connector (see :

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So far we simply used PIO mode, but we would like to extend our controller so that it can handle Ultra DMA.

The problem is that we just realized that this protocol is somewhat tricky, more specifically we are concerned on how to implement the "source synchronous" side of the protocol expecially for read operation (see below).

________ ____________ ________ __________ \ / \ / \ / Data X Valid Data X ?????? X Valid data ________/ \____________/ \________/ \_________

| _______________________ | DStrobe |/ \| ________________/| |\________ | |

DStrobe and DATA are both sourced by the hard drive side.

According to the ATA-6 spec (or at least what I understood from it) the data should be sampled on a rising and falling edge of DStrobe.

We believe that the most simple solution would be to use DStrobe as a clock signal to sample the data (for both edges)in some registers, then re-synchronize these registers with the FPGA system clock with another register stage.

However, we are not sure that this the best (or even a good approach). Besides, we realized (too late, of course) that the DStrobe pin of the IDE drive is not connected to a GCK pin of our FPGA, making it probably difficult to use this signal as a clock ...

Would anybody have somme hints and or advices on how to tackle this issue ??

Thank you very much in advance.

Steven Derrien

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