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Signed Multiplication in a Virtex-II Multiplier.

I am trying to construct a 6x6 signed multiplier using the Virtex II block multipliers. I know that the V-II multipliers are inherently a 2's complement signed multiplier. However, my question is - by how much should I sign-extend the inputs?

Example: Input A - 6 bit Input B - 6 bit Output B- 12 bit

Should I connect the remaining ports of the multiplier input (A(7:18)) to A(6) or just A(7:12) to A(6)? The handbook suggests that the sign-extension of the inputs is done till the width of the output. Is this enough or should I do it till the physical width of the multiplier?

Thanks

Anil

Reply to
Anil Khanna
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If you use Xilinx IP Core A - 6 bit B - 6 bit B- 12 bit is enough

"Anil Khanna" ?ÈëÏû?ÐÂÎÅ :3f906a1c$ snipped-for-privacy@solnews.wv.mentorg.com...

I

sign-extension

should

Reply to
Peng Cong

If you use Xilinx IP Core A - 6 bit B - 6 bit B- 12 bit is enough

"Anil Khanna" ?ÈëÏû?ÐÂÎÅ :3f906a1c$ snipped-for-privacy@solnews.wv.mentorg.com...

I

sign-extension

should

Reply to
Peng Cong

Thanks for the reply.

However, I am not using the Xilinx Coregen! Anyways, I figured out the answer to this question and now I have another Q.

The handbook claims that there are certain submodules (of the MULT18X18S) available for use. These are submodules like MULT4X4 etc. How does one get access to this and what is the primitive name?

Anil

block

should

to

Reply to
Anil Khanna

Are you sure? I look into the datasheet of Multiplier Generator V6.0, did not see anything about submodules

"Anil Khanna" ?ÈëÏû?ÐÂÎÅ :3f923e9f$ snipped-for-privacy@solnews.wv.mentorg.com...

Q.

Reply to
Peng Cong

another

MULT18X18S)

get

(A(7:18))

or

Reply to
Anil Khanna

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