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Signed addition

Ah! A statement that it's homework! Good! This means that I won't give you hell, or ignore the post. Unfortunately it also means I'll only ask questions -- but hopefully they'll be helpful questions.

Such a number format would make sense in some cases - as soon as you get off the beaten path of microprocessors and into FPGA design anything can happen.

Is that the least-complicated way to do it (this is a true question -- I don't know)? When you add things by hand you use a sign + magnitude notation -- do you convert to 9's complement, add, wrap the carry, then convert back to sign + magnitude, or is there something else you do?

Check out the 74181, by the way.

This is a 1's complement thing, isn't it? Is your last carry ever affected by your first carry? If so, what happens to your circuit?

If you came up with it I think you already know the answer to that.

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Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
Reply to
Tim Wescott
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It might. For example, if the number was to be displayed or printed or transmitted as human-readable ASCII, that would be a good format. Two's complement would require work to display a negative number correctly.

How about you do a mental/pen and paper simulation with test cases that are in all 4 quadrants and tell us whether it works.

Best regards, Spehro Pefhany

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Reply to
Spehro Pefhany

Hi,

I need to add too signed binary numbers which are in a format such that the MSB is the sign and the rest of the bits are the number's absolute value. The addition can be done with combinatorial logic and must be implemented with 74-series logic. Using such number format probably doesn't make much sense, but homework assignments rarely do :)

So what I planned was to make a circuit that first converts the numbers to 1's complement if the sign bit is 1 with XOR gates and then adding them together. The carry out of the last adder must be connected to the carry in of the first adder, right? The result is converted back to the original number format.

Will this work?

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Juha Turunen (turunen(at)iki.fi) elpuri@IRC | The problem with the global
Torikatu 5A4, 53900 Lappeenranta, Finland   |  village are all the global
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Reply to
Juha Turunen

Oh, don't mind Fred -- he's one of our resident cranks. I think he must flip a coin each time or something, because he's helpful about 1/2 the time.

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Tim Wescott
Wescott Design Services
http://www.wescottdesign.com
Reply to
Tim Wescott

It makes sense in terms of testing your knowledge of arithmetic operations on various forms of binary number representations, and in your case it looks like you fail. Go back and review the material until you understand it, then answer the question yourself.

Reply to
Fred Bloggs

Thanks for your answer, though I found the other ones much more educational. I know a lot of people try to get other on USENET to do their homework. That's why I came up with a solution and thought about asking other people, if I should even bother trying it out.

Next time someone asks something maybe you could try to be more constructive like the other ones that replied or maybe not reply at all instead of wasting two minutes of your life writing a semi-polite f*ck you.

--
Juha Turunen (turunen(at)iki.fi) elpuri@IRC | The problem with the global
Torikatu 5A4, 53900 Lappeenranta, Finland   |  village are all the global
GSM: 040-7092525, http://iki.fi/turunen/    |   village idiots.
Reply to
Juha Turunen

If the magnitude was 8-bit, the one's complement of x would be 255-x. If you write equations for the output of your circuit in at least three of the four quadrants, you'll see the answer.

Reply to
Andrew Holme

Is that what you call a "solution"- a little piss ant vague verbal description?

Ok- here's a not-so-polite f_ck you. Now for the not-so-constructive criticism: it is clear that you are little poof punk bs artist, you are a slouch and a shirker, as well as an uneducable low life enrolled in the wrong course of study.

>
Reply to
Fred Bloggs

I don't know exactly what you mean but ... You don't have to actually do the conversion if the sign bit is a 1. Connect to your XOR gate a control signal 0 or 1. With control enabled if your number is negative the conversion is automatic, if its not it just passes through unchanged.

Yes which is a bit tedious with 1s complements , because the MSB must be end around carried and added to produce the right result. With a 2s complement you'd just have to discard the end around carry easily implemented by connecting a NAND gate from the MSB of the input to the MSB of the output.

Yes but there are faster and less complex approaches then cascading adders. If you want top marks include an overflow detector. ie overflow = carryin XOR carryout. Good luck

Reply to
lemonjuice

Let it alllllll out.. Everything's gonna be just fine... :)

--
Juha Turunen (turunen(at)iki.fi) elpuri@IRC | The problem with the global
Torikatu 5A4, 53100 Lappeenranta, Finland   |  village are all the global
GSM: 040-7092525, http://iki.fi/turunen/    |   village idiots.
Reply to
Juha Turunen

Like I said- wise ass punk poof...

Reply to
Fred Bloggs

Yes, but it would be better to use 2's complement, because then you don't have to worry about the carry around. Here's how. The three different ways to represent -5 in 8 bits are as follows.

In signed-magnitude: 10000101 In signed-1's complement representation: 11111010 In signed-2's complement representation: 11111011

All positive numbers are represented the same. A signed-magnitude negative number can be changed to a signed-2's complement by keeping the leftmost bit

1, inverting the 7 remaining bits, and then adding 1 to the 7 bit group. The same procedure will also convert signed-2's complement back to signed magnitude. After both numbers are converted to signed-2's complement, simple add both 8 bit groups which include the signs together. Ignore any sign carry out in all cases. If leftmost bit of the result is 1, then convert it back to signed-magnitude. If the two numbers have different signs, then no overflow can possibly occur. If the two numbers have the same sign, then the result must also have the same sign, or an overflow has occurred. Hope that helps. Ratch
Reply to
Ratch

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