mux / serdes

Dear newsgroup readers,

I am currently working on a multiplexer design in VHDL. For the time being the design should run on a Xilinx Virtex II FPGA but actually I am not concerned about any target device later on. My question is more general. What I want to do is multiplex four input signals into one output signal, meaning that there are four parallel inputs that should merge into one serial output. Therefore the output must be four times faster than the input, right? I see problems in generating the faster clock out of the master clock of the slower inputs, that means I HAVE TO provide the fast clock for the serial output right away and then transform it back to the slower to handle the input, is that right? What's more I want to multiplex the signals byte-wise. How can that be achieved WITHOUT wasting a great amount of registers? And how to manage the data being transfered between the two clock domains?

Regards, Leroy

You're right if you say you strictly want to go device-independent. But this quite simple problem really seems worth looking at the individual target datasheets. The problem is not solvable within VHDL itself. Often the FPGAs provide some DPLL with builtin clock-multiplier. So use those macrocells. OR (and even more technology-dependant) you can feed two clock-signals into an exor, with one signal being artificially delayed by e.g. 2, 4 or 6 NOTs. EXORs probably have an even longer delay. Whatever the gatelist offers. But be sure that the gates don't get optimized away (VHDL device/synthesizer specific macros). The EXOR output will then be CLKx2. If you need 4 inputs use this structure twice. (and validate all timings!)

You're targeting an Virtex II. Don't worry about some single registers. Get the byte-trigger from somewhere - if its a serial COM-port recognize the STOP-bit. Definitely try to derive all clocks from a single clock source. In case you need to traverse clock domains use min. 2 sequential FlipFlops to up-/downsample the signal. I have seen 1E-5 bit errors on a 7ns Altera device with a single FlipFlop.