LVDS driver in SERDES

TI and national uses start bit and stop bit. If the data runs continuously, how can the clock be embedded in them.

Part numbers would be more useful.

If the data doesn't run continuously, how much data is lost while the clock recovery circuit in the receiver is busy locking to it?

Have fun,

Marc

TI - SN65LV1021 / SN65LV1212 NS- DS92LV16

I guess the 1st few cycles will be lost and till the lock is held, there should be no problem. I am more confused abt embedding the clock now.

Whose SERDES are you talking about- the straightforward ones don't know anything about any "data group", they run continuously.

Ah, you are talking about the low-speed (100-400 Mbps) 1:10 LVDS bus extenders. They do use a start/stop bit setup to keep word alignment across the link, but the device does all that for you - so I'm not sure what your original question was about.

More than a few... if you'll notice in the SN65LV1021 data sheet, there is a whole page dedicated to the topic of synchronization between the transmitter and receiver. The "rapid synchronization" mode takes

transitions at the LVDS input, it attempts to lock to the embedded clock information. The deserializer LOCK output remains high while its PLL locks to the incoming data or SYNC patterns present on the serial input."

In reading the datasheet, there almost seems to be an implication that the REFCLK for the receiver must be the exact same frequency as TCLK - so the "clock recovery" may just be used for phase aligning the PLL'ed REFCLK with the incoming data.

Marc

That clock is supposed to be CW, the data is parallel in, what do you think you're going to do- drill a hole in the package to access an internal node? The datasheet information is self-evident, how is it possible for anyone to become confused.