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LVDS driver in SERDES

SERDES has a start bit and a stop bit before and after a data group. While driving this signal with a LVDS driver,Since start bit and stop bit are either always high or low, there is no difference in the voltage levels between the signal at a LVDS driver output. In a normal LVDS driver, the output is got across a resistor whose current depends on the difference in the 2 voltage levels. Since at the start bit and stop bit, the difference is 0,the current is also 0. So I get a voltage level of 0V or power supply voltage instead of a LVDS level of 1.4V or

1V at the RXer end for the start/stop bit.

What can I do to get the LVDS voltage level at the start and stop bit?

Reply to
Iterativeend
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TI and national uses start bit and stop bit. If the data runs continuously, how can the clock be embedded in them.

Reply to
Iterativeend

Part numbers would be more useful.

If the data doesn't run continuously, how much data is lost while the clock recovery circuit in the receiver is busy locking to it?

Have fun,

Marc

Reply to
mrand

TI - SN65LV1021 / SN65LV1212 NS- DS92LV16

I guess the 1st few cycles will be lost and till the lock is held, there should be no problem. I am more confused abt embedding the clock now.

Reply to
Iterativeend

Whose SERDES are you talking about- the straightforward ones don't know anything about any "data group", they run continuously.

Reply to
Fred Bloggs

Ah, you are talking about the low-speed (100-400 Mbps) 1:10 LVDS bus extenders. They do use a start/stop bit setup to keep word alignment across the link, but the device does all that for you - so I'm not sure what your original question was about.

More than a few... if you'll notice in the SN65LV1021 data sheet, there is a whole page dedicated to the topic of synchronization between the transmitter and receiver. The "rapid synchronization" mode takes

6+1026 TCLK cycles. The "random-lock" mode presumably takes even longer.

transitions at the LVDS input, it attempts to lock to the embedded clock information. The deserializer LOCK output remains high while its PLL locks to the incoming data or SYNC patterns present on the serial input."

In reading the datasheet, there almost seems to be an implication that the REFCLK for the receiver must be the exact same frequency as TCLK - so the "clock recovery" may just be used for phase aligning the PLL'ed REFCLK with the incoming data.

Marc

Reply to
mrand

That clock is supposed to be CW, the data is parallel in, what do you think you're going to do- drill a hole in the package to access an internal node? The datasheet information is self-evident, how is it possible for anyone to become confused.

Reply to
Fred Bloggs

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