Hi, I am having trouble with the code generated from SelectLink Verilog code generator. Has anyone successfully used the code generated from this web site?
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Here is the trouble I am having: There is no constraints or simulation files. So I wrote a simple loopback testbench connecting the Xmt side to the receive side of the bi-directional(lvds 32 to 8) Select link code generated. The functional simulations works okay. But, the simulation done after map does not work. I am assuming this might be the problem with the lack of constraints. Appreciate any help on this issue. Thanks much.
Thomas