Master's Project

Consider a "completable" project.

If you know verilog, consider a synchronous rtl design and a simulation testbench to prove that it works.

Consider targeting your tested rtl code to several FPGA devices using synthesis and compare utilization and fmax, from the synthesis reports. This will prove that your code is portable without having to build circuit boards.

-- Mike Treseler

Engineering student. I have done some courses on Digital Design, Verilog, Computer Architecture and Microprocessor Design. I'll love to try my hands on FPGA but I have no idea where to start. I've checked Xilinx site but had difficulty focusing on varieties of choices. I need some ideas on project that can be done in 4-5 months' timeframe, with next to none budgetry, not to mention skill and graduate level req...

How about putting together a RISC processor, and as an extension demonstrate the effect of pipelining on throughput.

Choose a simple architecture:

say A and B reg feeding into an ALU which has only a few opcodes (well preferrably 2,4,8 or 16 opcodes), the ALU feeds onto bus. Have a simple memory interface and at the heart a state machine, which you code up behaviourally perhaps.

If you want the FPGA slant look up on Xilinx.com the picoblaze processor, written by Ken Chapman, also known as KCPSM (officially K constant programmable state machine, but in the KC prob stands for Ken Chapman). Compare your processor with Picoblaze in terms of:

I think there are plenty of angles here. And your background in computer architecture is a good foundation.

That reminds me. Lois might find inspiration in the last two sections of "Hands On Computer Architecture: Teaching Processor and Integrated Systems Design with FPGAs"

Jan Gray