Scoping a glitch

If I make some assumptions about how the LUTs work internally, I get the same conclusion as you. Working with Peter's conditions, something like an xor gate would definitely not be safe, but a 2 to 1 mux might be.

Regards, Allan

Reply to
Allan Herriman
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We were recently playing with a Spartan 3, to see how narrow a pulse we could count, using LVDS inputs feeding the first flop of a ripple counter. 1 ns seemed to work OK.

We have seen slow input edges with a tiny amount of noise clock on the wrong edge. Even CCLK does this!

Output edges are similarly screaming fast, sub-ns.

One can also do serious amounts of logic and get jitter in the 10s of ps RMS.

They should give us a slow+schmitt input option.

John

Reply to
John Larkin

I would like to spend the time to spit my glitchy clock out a LVDS pair to see if that can resolve the internal glitch.

Certainly a LVCMOS33 can't, or just barely shows a hint of inflection.

I also need to see if it's an asynchronous edge from another process happening at the same time as the glitched clocks.

Yeah, I was thinking that too. A little too much to ask for I suppose.

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Mr.CRC
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Reply to
Mr.CRC

y.

What will you do with that information? Will it impact how you fix the problem?

I/O features are market driven. Designs that use slow inputs are mostly older technology that can afford to provide a buffer to sharpen up the edge externally to the FPGA. Designs that use 1.8 volt IOs or LVDS, etc, are higher technology which often need the more current FPGA densities and features and are the apps that sell the higher margin parts. Remember, the FPGA market is still driven by communications apps. The industrial controls and most other apps don't even show on the FPGA vendors' radar screens. So these apps get what the FPGA makers provide and like it... or not... but that's what they get anyway.

What about the makers of the SOC parts like Cypress and Actel, do they include any Schmitt inputs?

Rick

Reply to
rickman

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