This is from the LTC1660 data sheet:
CLR (Pin 11): Asynchronous Clear Input. All internal shift and DAC registers are cleared to zero at the falling edge of the CLR signal, forcing the analog outputs to zero scale. CMOS and TTL compatible.
So, why does an async input act "at the falling edge"?
This is typical for the digital spec sections of ADC and DAC data sheets. It's unclear whether things are level or edge sensitive, active high or low, and often what things actually do.
Same sort of thing for the strobe input on LTC1596. It's not absolutely clear if this is level or edge sensitive.
All the mixed-signal people seem to do this sort of thing.
John